Proceedings Article10.1109/BCTM.2015.7340548
A 17 GHz programmable frequency divider for space applications in a 130 nm SiGe BiCMOS technology
Frank Herzel,Johannes Borngraber,Arzu Ergintav,Maciej Kucharski,Dietmar Kissinger +4 more
- 03 Dec 2015
- pp 133-136
TL;DR: In this paper, a programmable frequency divider for fractional-N frequency synthesizers is presented, and the quantization noise folding in a fractional N PLL can be reduced greatly if a prescaler between VCO and programmable divider can be avoided.
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Abstract: A programmable frequency divider for fractional-N frequency synthesizers is presented. The input frequency range is from DC to 17GHz for divider ratios from 16 to 255. We show by analysis and time-domain simulations that the quantization noise folding in a fractional-N PLL can be reduced tremendously, if a prescaler between VCO and programmable divider can be avoided by using this high-speed divider. The programmable divider was manufactured in a 130nm SiGe BiCMOS technology. Robust operation is obtained from a supply voltage VCC=3D2.3-3.9 V. The measured divider phase noise floor for a 100 MHz output signal is as low as −156dBc/Hz. The chip occupies 1.7 mm2 including bondpads and draws 154mA from a 2.3V supply.
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Citations
An integrated frequency synthesizer in 130 nm SiGe BiCMOS technology for 28/38 GHz 5G wireless networks
Frank Herzel,Maciej Kucharski,Arzu Ergintav,Johannes Borngraber,Herman Jalli Ng,Jorg Domke,Dietmar Kissinger +6 more
- 01 Oct 2017
TL;DR: In this paper, an integrated frequency synthesizer for 28.7 GHz is presented, which is achieved at low phase noise by combining capacitive tuning and inductor switching in the voltage-controlled oscillator.
13
A Programmable Frequency Divider With a Full Modulus Range and 50% Output Duty Cycle
TL;DR: A programmable frequency divider with a full modulus range, 50% output duty cycle and low phase noise is presented and employs a novel programmable down-counter based on a modified D flip-flop with a load function.
Low-power and low-noise programmable frequency dividers in a 130 nm SiGe BiCMOS technology
Arzu Ergintav,Frank Herzel,Johannes Borngraeber,Herman Jalli Ng,Dietmar Kissinger +4 more
- 25 Jun 2017
TL;DR: The programmable frequency dividers' phase noise contribution referred to the output of a 10GHz PLL is lower than −108 dBc/Hz at 10 kHz offset and −116.5 dBc /Hz at 1MHz offset, which makes the dividers suitable for low-noise fractional-N phase-locked loops using a conventional CMOS phase-frequency detector.
8
Design and layout strategies for integrated frequency synthesizers with high spectral purity
Frank Herzel,Dietmar Kissinger +1 more
TL;DR: Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented and remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout.
X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology
TL;DR: In this paper , the authors presented a 9.4 GHz low-noise phase-locked loop (PLL) in 0.13μm SiGe BiCMOS technology for 5G applications.
1
References
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TL;DR: The silicon-germanium heterojunction bipolar transistor (SiGe HBT) as mentioned in this paper is the first practical bandgap-engineered device to be realized in silicon and has achieved state-of-the-art performance.
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A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology
TL;DR: In this article, a modular and power-scalable architecture for low-power programmable frequency dividers is presented, which consists of a 17-bit UHF divider, an 18-bit L-band divider and a 12-bit reference divider.
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A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800
B. De Muer,Michel Steyaert +1 more
TL;DR: In this article, a 1.8 GHz /spl Delta/spl Sigma/controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25/spl mu/m CMOS technology.
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Phase noise in digital frequency dividers
TL;DR: In this paper, a physical derivation of phase noise in source-coupled-logic frequency dividers is presented, taking into account both white and flicker noise sources and verified on two 32/33 dual-modulus prescalers integrated in a 0.35/spl mu/m CMOS process.
125
On the analysis of /spl Delta//spl Sigma/ fractional-N frequency synthesizers for high-spectral purity
Bram De Muer,Michel Steyaert +1 more
TL;DR: A fast, nonlinear analysis method is developed to swiftly and accurately examine the effect of nonidealities on the spectral purity of the synthesizer, with a focus on monolithic /spl Delta//spl Sigma/ fractional-N synthesizer design in CMOS with high spectral purity.
112