Book Chapter10.1007/978-1-4419-9542-1_20
3D-MAPS: 3D Massively parallel processor with stacked memory
Dae Hyun Kim,Krit Athikulwongse,Michael B. Healy,Mohammad M. Hossain,Moongon Jung,Ilya Khorosh,Gokul Kumar,Young-Joon Lee,Dean L. Lewis,Tzu-Wei Lin,Chang Liu,Shreepad Panth,Mohit Pathak,Minzhen Ren,Guanhao Shen,Taigon Song,Dong Hyuk Woo,Xin Zhao,Joungho Kim,Ho Choi,Gabriel H. Loh,Hsien-Hsin Lee,Sung Kyu Lim +22 more
- 03 Apr 2012
- pp 188-190
186
TL;DR: 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM.
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Abstract: Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5×5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.
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Citations
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
Amin Farmahini-Farahani,Jung Ho Ahn,Katherine Morrow,Nam Sung Kim +3 more
- 01 Feb 2015
TL;DR: This paper proposes near-DRAM acceleration (NDA) architectures, which process data using accelerators 3D-stacked on DRAM devices comprising off-chip main memory modules, substantially reducing energy consumption and improving performance.
338
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
Seth H. Pugsley,Jeffrey Jestes,Huihui Zhang,Rajeev Balasubramonian,Vijayalakshmi Srinivasan,Alper Buyuktosunoglu,Al Davis,Feifei Li +7 more
- 23 Mar 2014
TL;DR: A number of key elements necessary in realizing efficient NDC operation are described and evaluated, including low-EPI cores, long daisy chains of memory devices, and the dynamic activation of cores and SerDes links.
Transparent offloading and mapping (TOM): enabling programmer-transparent near-data processing in GPU systems
Kevin Hsieh,Eiman Ebrahimi,Gwangsun Kim,Niladrish Chatterjee,Mike O'Connor,Nandita Vijaykumar,Onur Mutlu,Stephen W. Keckler +7 more
- 18 Jun 2016
TL;DR: Extensive evaluations across a variety of modern memory-intensive GPU workloads show that TOM significantly improves performance compared to a baseline GPU system that cannot offload computation to 3D-stacked memories.
290
Data reorganization in memory using 3D-stacked DRAM
Berkin Akin,Franz Franchetti,James C. Hoe +2 more
- 13 Jun 2015
TL;DR: A two pronged approach for efficient data reorganization is presented, which combines a proposed DRAM-aware reshape accelerator integrated within 3D-stacked DRAM, and a mathematical framework that is used to represent and optimize the reorganization operations.
Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems
TL;DR: The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems.
128
References
3D-Stacked Memory Architectures for Multi-core Processors
Gabriel H. Loh
- 01 Jun 2008
TL;DR: This work explores more aggressive 3D DRAM organizations that make better use of the additional die-to-die bandwidth provided by 3D stacking, as well as the additional transistor count, to achieve a 1.75x speedup over previously proposed 3D-DRAM approaches on memory-intensive multi-programmed workloads on a quad-core processor.
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
G. Van der Plas,Paresh Limaye,Igor Loi,Abdelkarim Mercha,Herman Oprins,C. Torregiani,Steven Thijs,Dimitri Linten,Michele Stucchi,G. Katti,Dimitrios Velenis,Vladimir Cherman,Bart Vandevelde,V. Simons,I. De Wolf,Riet Labie,D. Perry,S Bronckers,N. Minas,Miro Cupac,Wouter Ruythooren,J. Van Olmen,Alain Phommahaxay,M. de Potter de ten Broeck,A. Opdebeeck,Michal Rakowski,B. De Wachter,Morin Dehan,Marc Nelis,Rahul Agarwal,Antonio Pullini,Federico Angiolini,Luca Benini,Wim Dehaene,Youssef Travaly,Eric Beyne,Pol Marchal +36 more
- 18 Oct 2010
TL;DR: Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3- D SoCs at low area and power and digital gates can directly drive signals through TSVs at high speed and low power.
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Xiangyu Dong,Yuan Xie +1 more
- 19 Jan 2009
TL;DR: The design estimation method for 3D ICs at the early design stage is studied, and a cost analysis model is proposed to study the cost implication for 3d ICs, and address the following cost-related problems related to3D IC design.
173
TSV manufacturing yield and hidden costs for 3D IC integration
John H. Lau
- 01 Jun 2010
TL;DR: In this article, the authors focus on the TSV manufacturing yield and hidden costs of 3D integration and a 3D IC roadmap is provided, with a focus on 3D Si integration.
164
Neuromorphic vision chip fabricated using three-dimensional integration technology
Mitsumasa Koyanagi,Yoshihiro Nakagawa,K. W. Lee,T. Nakamura,Y. Yamada,K. Inamura,Ki-Tae Park,Hiroyuki Kurino +7 more
- 05 Feb 2001
TL;DR: In this paper, a 3D integration technology for image processing and pattern recognition with parts of functions of the retina and visual cortex using silicon is presented. And the three-dimensional (3D) integration technology achieved an image processing, pattern recognition, and pattern classification system using parts of functional units of the human brain using silicon.
137
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