3D and Microprocessors
Pat Morrow,Sriram Muthukumar +1 more
- 25 Nov 2008
- pp 651-674
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About: The article was published on 25 Nov 2008.
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References
Die Stacking (3D) Microarchitecture
Bryan Black,Murali Annavaram,Ned Brekelbaum,John P. Devale,Lei Jiang,Gabriel H. Loh,Don McCaule,Pat Morrow,Donald W. Nelson,Daniel Pantuso,Paul Reed,Jeff Rupley,Sadasivan Shankar,John Paul Shen,Clair C. Webb +14 more
- 09 Dec 2006
TL;DR: This research study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack.
684
Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology
TL;DR: In this article, the authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology, and demonstrate the functionality of stacked 4-MB SRAMs.
188
A CMOS-compatible process for fabricating electrical through-vias in silicon
P.S. Andry,Cornelia K. Tsang,Edmund J. Sprogis,Chirag S. Patel,Steven L. Wright,B. C. Webb,Leena Paivikki Buchwalter,Dennis G. Manzer,R. Horton,Robert J. Polastre,John U. Knickerbocker +10 more
- 05 Jul 2006
TL;DR: In this article, a novel approach to fabricating robust though-vias in silicon is described, and two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus.
110
Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures
Anna W. Topol,Bruce K. Furman,Kathryn W. Guarini,Leathen Shi,Guy M. Cohen,G.F. Walker +5 more
- 01 Jun 2004
TL;DR: In this paper, the authors describe several critical aspects of wafer scale or die level bonding to demonstrate: (1) low temperature bonding for planar layer interconnections; (2) low-temperature bonding for non-planar layer sealing; (3) alignment and transfer of process sub-assemblies such as BEOL wiring, MEMS cavity or active device structures; and (4) integration methodology for fabrication of these layer stacks into 3D circuits and MEMS.
83
Calibration of Rent's rule models for three-dimensional integrated circuits
TL;DR: It is found that the Rahman model predicts wirelengths accurately (to within 20% of placement and of routing, on average), and some areas for minor improvement to the model are suggested.
57