Journal Article10.1002/J.1538-7305.1977.TB00180.X
1a processor: Control system
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TL;DR: This article contains a description of the central control, input/output subsystem, processor-peripheral interface, master control console, and the interunit communication bus system.
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Abstract: This article contains a description of the central control, input/output subsystem, processor-peripheral interface, master control console, and the interunit communication bus system. The units are discussed in a manner which highlights comparison of features with No. 1 ess and stresses those features which are most important in meeting the stringent reliability objectives.
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Citations
Fault-tolerant design of local ESS processors
W.N. Toy
- 01 Oct 1978
TL;DR: Pertinent processor architecture features used to achieve ESS reliablity objectives are discussed and a detailed discussion of the maintenance design of the 3A Processor is also included.
148
Architecture of fault-tolerant computers: an historical perspective
D.P. Siemwiorek
- 01 Dec 1991
TL;DR: In this article, the authors survey the approaches and techniques used to improve system reliability, and present a three-dimensional design space for comparing fault-tolerant systems and a detailed description is provided for a dozen systems evenly distributed throughout the design space.
67
Fault-Tolerant Computing
TL;DR: The chapter focuses on reliability estimation, which is a process of predicting from available failure-rate data the achievable reliability of a part, subsystem, or system and the probability of meeting its objectives for a specified application.
64
No. 4 ESS: Maintenance software
TL;DR: To ensure quality service, a toll switching system must be able to meet very stringent dependability and maintainability requirements and to meet these requirements a large package of maintenance software has been developed.
17
Patent
Method and apparatus for identifying faulty communications circuits
Charles Dan Gavrilovich
- 07 Apr 1983
TL;DR: In this article, a method for detecting defective communications circuits in a telecommunications system is proposed, in which communications circuits are arranged in groups according to destination and unacknowledged communications are counted for each group.
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