Abstract: Spin accumulation induced in p-type germanium from Fe/MgO tunnel contacts is studied as a function of hole concentration p (1016–1019 cm-3). For all p, the contacts are free of rectification and Schottky barrier, guaranteeing spin injection into the Ge and preventing spin accumulation enhancement by two-step tunneling via interface states. The observed spin accumulation is smallest for nondegenerate doping (p~1016 cm-3) and increases for heavily doped Ge. This trend is opposite to what is expected from spin injection and diffusion theory. For heavily doped Ge, the observed spin accumulation is orders of magnitude larger than predicted.

Abstract: We have established low loss of single-mode Si waveguide fabrication process with variable-shaped-beam (VSB) EB lithography. The attenuation loss and bending loss are 1.5dB/cm in 480nm x 220nm core dimension and 0.08dB/turn in 4μm bending radius, respectively. This technology consists of multiple exposure technique using pattern segmentation software and EB lithography technology with lower line edge roughness (LER) and controlled high resolution process conditions.

Abstract: In this paper, the effect of the active layer thickness and temperature on the switching kinetics of GeS2-based conductive bridge memories is addressed through electrical characterization. Results are explained in terms of a thermally and field driven ion hopping model for reversible resistance switching. The combined analysis reveals that at high temperature the set voltage and the set resistance decrease. Furthermore, the study suggests that applying the same reset condition, for GeS2 thicknesses lower than 50 nm, the conductive filament is almost dissolved, while for thicker layers a portion of the filament still remains.

Abstract: Full three-dimensional simulation of DNA detection by ion-sensitive field-effect transistor technology is presented. DNA conditions for improving the sensing characteristics, namely, increased hybridization signal, are clarified. Poisson's equation is solved using a full three-dimensional finite element method for the model, where the model space consists of an electrolyte, DNAs, a self-assembled monolayer, and an insulator. The flatband voltage shift due to the hybridization of randomly positioned and oriented DNA is similar to experimental data, and indicates the possibility of experimental prediction. We examine the effects of DNA position and orientation on flatband voltage shift, and it is noted that the hybridization signal becomes largest when the DNAs are tilted 90° and distributed at equal intervals. It is also noted that a large hybridization signal can be obtained when upright DNAs are tightly immobilized even if it is difficult to tilt the DNAs.

Abstract: The electrical characteristics of 4H-SiC p–i–n diodes with 8H-type in-grown stacking faults are investigated. The 4H-SiC p–i–n diodes have epilayers with a low Z1/2 center density formed by carbon implantation. The forward voltage drops of the 4H-SiC p–i–n diode with 8H-type in-grown stacking faults are larger than those of the 4H-SiC p–i–n diode without an 8H-type in-grown stacking fault. The differential on-resistance of the 4H-SiC p–i–n diode with 8H-type in-grown stacking faults is larger than the drift resistance of the drift layer calculated from the doping density and thickness of the drift layer. A large number of electrons are trapped at 8H-type in-grown stacking faults, and the effective carrier density decreases compared with the doping density.

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Abstract: In this work, a high-performance compound semiconductor tunneling field-effect transistor (TFET) based on germanium (Ge)/gallium arsenide (GaAs) heterojunction with a tunneling-boost layer is investigated. The tunneling-boost layer in the source-side channel alters the energy band-gap structure between the source and the channel, which affects current drivability considerably. It is shown that controlling the lengths of the boosting layer (thin n+ GaAs layer) and lightly doped p-type channel (p-GaAs) also has substantial effects on adjusting Vth without complications arising from shifting metal workfunction. Furthermore, we evaluate device performances such as on-state current (Ion), subthreshold swing (S), intrinsic delay time (τ), and cut-off frequency (fT). The proposed TFET with an n-GaAs length of 12 nm showed an S of 27 mV/dec and approximately 3 times higher Ion than that of the device without a boosting layer. Moreover, it is confirmed from the extracted excellent radio-frequency (RF) parameters that the proposed device is suitable for RF applications.

Abstract: System-In-Package (SIP) enables flexible and low cost integration of multiple components such as memory, logic or passives in a single package. However, SIP performances are today limited for high performances applications such as FPGA, processor or GPU in which high bandwidth communication between the elements of the system is required. The use of an intermediate carrier such as Silicon Interposer between IC chips and substrate resolve the bandwidth bottleneck by increasing the I/Os number. Indeed, Si Interposer combines fine pitch μBumps and high density routing for fast and high bandwidth interconnection between mounted chips. Low cost semi-additive electrochemical plating process (ECP) is often used for interposer routing processing [1]. Damascene process is an alternative allowing for an improved reliability (use of barrier between Cu and dielectric) and better line pitch scalability [2]. However, the use of thin lines characteristic of standard damascene technology such as 65 nm Back-End-Of-Line (BEOL), impact overall signal transmission performances because of their relative high resistance compare with ECP approach. In this work, impacts of Cu lines dimensions and line neighboring onto system bandwidth and crosstalk are first simulated. The output allows for optimal performances interposer damascene interconnect which process and characterization are described in a second part.

Abstract: 1. Introduction The invention of the High-Electron Mobility Transistor (HEMT) revolutionized the world of high-frequency electronics [1]. First on GaAs, then on InP and more recently on GaN, HEMTs have steadily achieved higher levels of performance in terms of high frequency gain, noise and power. Today, InAs HEMTs on InP exhibit the best balanced high-frequency response (high f T and high f max) of any transistor technology [2]. InAs HEMTs are uniquely poised to attain the first true THz transistor (both f T and f max >1 THz). This paper reviews the evolution of HEMTs along their path towards THz operation and discusses steps to be taken in order to attain this ultimate prize.

Abstract: 1 Frontier Research Center, Tokyo Institute of Technology, 2 Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502, Japan 3 Honors Graduate Program for Nanotech/Sciences, University of Tsukuba, 4 Graduate School of Pure and Applied Sciences, University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8573, Japan 5 Institute for Nanoscience and Nanotechnology, Waseda University Shinjuku, Tokyo 169-8555, Japan Phone: +81-45-924-5847, Email: yan.w.ab@m.titech.ac.jp

Abstract: Using a novel Voronoi method that can physically consider the interaction between neighboring grains, we invesgate and compare the impact of work-function variation (WFV) on FinFET and UTB SOI devices. Our study indicates that for a given electrostatic integrity (EI) and total effective gate area, the FinFET device exhibits better immunity to WFV than the UTB SOI counterpart. We further show that, unlike other sources of random variation, the WFV cannot be supressed by EOT scaling.

Abstract: The impact of two post-growth processes, namely, C+-implantation/annealing process and thermal oxidation/annealing process, on trap concentrations in thick n-type 4H-SiC epilayers was studied for both Si- and C-face. Conditions such as the implantation dose and annealing temperature of the C+-implantation/annealing processes were optimized for Si-face epilayers, and consequently the Z1/2 center was eliminated up to 100 μm or more, and the minority carrier lifetime reached 13 μs while maintaining a good surface morphology. The effect of the process conditions on the creation of new traps, including ON1 center, was also studied in both Si- and C-face epilayers. The ON1 center was introduced in both Si- and C-face by two post-growth processes, although the concentration was found to vary according to the polar face and the post-growth processes. The mechanism of the different impacts on Z1/2 center reduction and ON1 center creation by the two post-growth processes on Si- and C-face is discussed.

Abstract: 1 Sumitomo Bakelite Co., Ltd., 20-7 Kiyohara Industrial Park, Utsunomiya 321-3231, Japan 2 Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6909, E-mail: ito@lbc.mech.tohoku.ac.jp 3 New Industry Creation Hatchery Center, Tohoku University 4 Deptartment of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku University