Abstract: In order to explore thermal inertia of electronic components,dynamic temperature response characteristics of chips based on thermal power signals were identifiedAccording to step function response curves of chip's temperature,transfer functions of temperature at chip's key points were establishedRelationship between temperature shock to chips induced by thermal power signals and signal period was analyzed in detail,based on square wave signal and sine signal response curves of chip's temperatureThis work is helpful in improving the capability of electronic components to resist thermal shock and thermal fatigue

Abstract: Temperature is one of the key factors that affect the reliability of electronic circuits.Therefore,it is quite necessary to perform thermal design for switching-mode power supply(SMPS).The importance of thermal analysis of electronic system is elaborated,and technical characteristics of thermal design software are described.And finally,thermal simulation of an actual SMPS circuit using Flotherm is presented based on EDA tools in Flomerics.

Abstract: A digital decimation filter inΣ-ΔA/D converter for audio applications was designed.The filter has a multistage and multi-rate structure consisting of a cascaded-integrator-comb(CIC) filter,a compensation filter and two half-band filters.To reduce the number of multiplication units,coefficients of the filter were encoded by canonical -signed-digital(CSD).Filter code for testing was written in Verilog,and output of the 128-time oversampling 4- bit modulator was simulated with Simulink.Results showed that the filter had an SNR of 101 dB,which is suitable for high-end audio applications.

Abstract: An AES enciphered algorithm was proposed based on finite field operation unitDifferent key expansions were compared and analyzedA flexible structure for key lengths of 128-bit,192-bit and 256-bit was implemented by multiplexing the same module and control moduleBy using the integrated reconfigurable AES system, hardware logic units could be reducedThe circuit was simulated using Verilog HDL and synthesized based on 035-μm CMOS technologyResults showed that the system achieved a data throughput of 211 Gbps with a clock frequency of 180 MHz in AES-128 mode

Abstract: Mechanism of resistance variation of CrSi thin-film resistor was analyzed.Experiments were made on effects of annealing conditions on the stability of CrSi thin-film resistors,and optimal annealing conditions were obtained.As a result,the temperature coefficient of CrSi thin-film resistors was reduced from 0.001 ℃ to ±0.0001 ℃,thus greatly improving the stability of CrSi thin-film resistors.

Abstract: Sample and hold circuit was studied,and a second-order system simulation was made on gain-boots operational amplifier to obtain optimal parameters.A novel structure of bootstrap switch was presented,and a sample and hold circuit for 12-bit 50 MHz pipelined A/D converter was designed and implemented in SMIC's 0.35 μm mixed-signal CMOS process.Test results showed that the proposed sample and hold circuit fulfilled the requirements of 12-bit 50 MHz pipelined A/D converter.

Abstract: A new dynamic phase/frequency detector(PFD) was designed for phase-locked loop(PLL) to enable fast frequency acquisition.Based on conventional structure,the proposed PFD eliminates blind area by delaying pre-charge of the dynamic D-type flip-flop with switch,to prevent edge loss during reset time.Based on TSMC's 0.18 μm CMOS process,the circuit was simulated in Cadence Spectre.Simulation results indicated that the proposed PFD,which operated in the frequency range from 1 MHz to 2 GHz,accelerated lock acquisition of a test bench PLL by 40.3%.

Abstract: In order to meet the requirements of high speed FFT processors for OFDM system,a 128-point high efficiency FFT processor was designed using a mixture decimation-in-frequency algorithm of three radix-4 and radix-2.Based on modified radix-4 algorithm,ping-pong RAM design and super pipeline architecture,each part of the FFT processor was optimized for closer timing and better hardware / power consumption.Implemented in SMIC's 0.18 μm 1P5M CMOS technology,the FFT processor operates at 66 MHz with 354.728 mW of power,and it occupies a chip area of 5.2075 m2.

Abstract: A novel ALU architecture-based FIR filter was designed,in which convolution operation was realized with memory and counters.With increasing order of FIR filter,logic gate counts remain unchanged,and memory capacity increases linearly,rather than exponentially as in conventional distributed arithmetic(DA) architecture.Consequently,equivalent logic gate counts decreased dramatically in ALU-based FIR filter.FPGA synthesis results show that,when the order of filter is greater than 64 taps,the proposed circuit has far less equivalent logic gate counts than the conventional DA approach.

Abstract: A 10-bit 100 MHz 2-channel time-interleaved pipelined A/D converter for IF receiver in 3G wireless communication was designed and implemented in 0.18-μm HJTC CMOS process.The ADC consumes less than 70 mW of power from 3.3 V supply.Op-amp sharing and telescopic structure were used to reduce power consumption of the ADC.Linearity of interleaved ADC is limited by offset mismatch,gain mismatch and time skew mismatch of channels.In this circuit,op-amp sharing,increasing accuracy of every channel and global passive sampling were adopted to reduce effects of these mismatches.Also,linearity deterioration caused by charge injection of the output switch and crosstalk of the off-switch capacitor was investigated,and non-idealities of the switches were removed by modifying clock signal arrangement,thus significantly improving linearity of the time-interleaved ADC.Results from post-layout simulation showed that the 2-channel time-interleaved ADC had an input signal bandwidth of 47.6 MHz at a sampling rate of 100 MSPS,and at the worst process corner(ss,120 ℃),it had an SFDR over 70 dB and an SNDR above 60 dB.

Abstract: Based on nonlinearity analysis of the preamplifier in folding and interpolation analog-to-digital converters (ADC),a novel differential difference preamplifier was designed to reduce interpolation nonlinearity.The circuit was simulated based on a 0.35 μm standard CMOS process with single 3.3 V supply voltage.Results showed that the new preamplifier could achieve a steady zero-crossing point output of 2.6 V in a wide input range from 0.85 V to 2.45 V,and it settled in 4.2 ns to an accuracy of 0.1%,which is useful for improving interpolation accuracy.

Abstract: In high-speed video system,timing skew and disorder caused by signal integrity issue and interconnection delay may lead to failure of the design.With increasing system clock frequency,the data valid window of time for reading and writing is getting smaller.It's necessary to perform a precise timing calculation and analysis to get a reliable reading and writing of data.This paper demonstrates constraint conditions that system timing should follow in detail,and describes simulation for guidance to practical wiring.Setting of constraint rules in actual system was also illustrated.

Abstract: A decomposition method for parabolic polynomial approximation was proposed to improve spurious free dynamic range(SFDR) of quadrature DDFS(Direct Digital Frequency Synthesizer) and decrease logic element occupancy. In this technique,sine(cosine) function was decomposed into several correlation functions,which was then calculated by using quadratic polynomial approximation.Compared to the conventional quadratic polynomial approximation, the proposed method could achieve a higher SFDR(up to 99.3 dBc) and a 20%reduction of logic element occupancy.Simulation results showed that,in high spectral quadrature-DDFS design,the proposed method is significantly superior in hardware cost,compared with the conventional approach.

Abstract: Charge-pump phase-locked loops(CP-PLL) features high speed,low power,low jitter and so on.Charge-pump,a Key block in PLL,is essentially a switched current source,which requires a precise and stable constant current source and an ideal switch.However,charge sharing and charge/discharge mismatch would occur during operation.By bootstrapping,charge sharing could be eliminated,and by using a current follower circuit,the charge/discharge current could could be well matched.Based on 2.5 V 0.25 μm CMOS process,a high performance charge pump was designed and simulated with Hspice.Simulation results showed that charge and discharge currents of the circuit were almost equal in the voltage range from 1.45 V to 2.0 V.

Abstract: In orthogonal frequency division multiplexing (OFDM) system,frequency offset destroys subcarrier's orthogonality and degrades system performance.A novel frequency offset estimation algorithm for OFDM systems was proposed based on a simple real training sequence.With only one training sequence,both integer and fraction frequency offsets could be efficiently estimated in time domain by using this algorithm.Simulation results showed that the proposed method,which was easy to realize,could improve the accuracy of frequency offset estimation.

Abstract: Based on in 035 μm CMOS process,a high performance amplifier was designed,which had an open loop gain of 84 dB,a-3 dB bandwidth of 12 kHz,a slew rate of 400 V/μs and a phase margin of 60°A telescopic structure was adopted for the two-stage cascade op-amp to achieve high voltage gain and large output swingA bandgap current source was used as bias circuit to meet the requirement of the operational amplifier

Abstract: Combined with device layout,laser microbeam irradiation of single event effect(SEU) in 2k SRAM memory cell and external circuit was carried out.SEU sensitive regions in SRAM were obtained.Laser energy threshold and equivalent LET threshold of different sensitive regions were determined.Single event latchup susceptibility in SRAM was also measured.Experiment results showed that SEU sensitive regions were at drain regions of the n-channel transistor in off-state,p-channel transistor in off-state and corresponding gate-controlled transistor.No single event latchup was observed in the expeiment,which indicated that epitaxy,source drain contact and adjustment of layout placement used for the device were effective for single event latchup hardening.

Abstract: A voltage feedforward technology for buck DC/DC switch-mode power supply(SMPS) controller was described. In this technology,duty cycle of PWM signal changes quickly with input supply voltage by adjusting the center amplitude of the triangular wave This technology can be used to effectively suppress effect of the input supply voltage variation on the output voltage,thus improving its stability.

Abstract: A 1.8 V 5.2 GHz LNA with ESD protection for WLAN 802.11a was implemented in IBM 0.18 μm CMOS process.The LNA was optimized based on the analysis of input impedance,voltage gain and noise figure of cascode LNA with inductive degeneration.Effects of ESD protection on LNA performance were discussed.Test results showed that the LNA had a forward gain of 10 dB,a noise figure of 4.29 dB,an IIP3 of 4 dBm and an S11 of-18 dB,and the circuit dissipated 6.5 mA of current from 1.8 V supply.