Abstract: Based on the sensitivity of node voltages, a novel fault dictionary method is developed for diagnosis of soft faults of tolerance analog circuits and nonlinear circuits, on the basis of a fault dictionary method for non tolerance linear circuits The principle of the mew method is described, and the method for establishment of the dictionary is discussedFinally, examples of simulation are also given

Abstract: The precise integration method is an effective method to analyze the transient response of lossy transmission lines By improving the precise integration method, the reactive loads can be analyzed easily in time domain, and the special transient problems such as short circuit and open circuit, which are difficult for the traditional method of FFT, can also be easily analyzed So, the efficacy of the precise integration method to analyze the transient response of transmission lines is improved greatly

Abstract: A new analog programmable device ispPAC10 of Lattice Company is introduced Its theory of operation, internal structure, input offset auto calibration and transfer function calculation are described in detail

Abstract: A direct digital frequency synthesizer (DDFS) used for QAM modulation and demodulation is presented, which synthesizes a 10 b output sine and cosine wave with a spectral purity of -70 dB at 50 MHz The synthesizer covers a bandwidth from dc to 25 MHz in 0 0116 Hz step with a corresponding switching speed of 20 ns and a tuning latency of 4 clock cycles An efficient look up table method for calculating the sine function is used, and a compressed algorithm that only calculates 1/8 sine function is employed to reduce the volume of ROM The whole digital system is implemented with Xilinx FPGA, and the digital signals are output through two D/A converters

Abstract: The Research and implementation of CMOS radio frequency integrated circuits will greatly broaden the application area of integrated circuits. Achievements in the research of radio frequency integrated circuits based on CMOS technology are presented in the paper. And problems associated are also discussed. Finally, several directions in the development of CMOS radio frequency integrated circuits are pointed out.

Abstract: WT5”BZ]A thermal analysis model for a packaged IC chip is proposed and the temperature-dependent circuit performance is analyzed Based on relaxation method, an electro-thermal simulator (Etsim) has been developed, which can be used to simulate the electro-thermal effects under uniform temperature distribution

Abstract: WT5”BZ]Measurements of transient effects of electronic devices and circuits are investigated Mechanisms of photocurrent in transistors are analyzed, and latch up and upset in CMOS circuits are studied Test on some types of transistors and CMOS circuits are carried out And some of the results are presented [WT5HZ]

Abstract: Estimation of maximum power dissipation is important in designing highly reliable VLSI systems However, maximum power estimation for CMOS circuits is essentially a combination optimization problem, which has exponential complexity in the worst case For large-scaled sequential circuits, due to the fact that the sequential relationship between the Primary Inputs and States must be considered, it is more CPU time intensive to exhaustively search for the optimal input patterns to induce maximum power In this paper, a novel approach is proposed to obtain a lower bound of the maximum power consumption using Genetic Algorithm (GA) Experiments with ISCAS-89 benchmark circuits show that our approach generates the lower bound with the quality that cannot be achieved using simulation-based techniques In addition, a Monte Carlo based technique to estimate maximum power dissipation is realized

Abstract: WT5”BZ]VHDL—AMS(VHDL 1076 1), an entirely integrated mixed signal design language, is presented in the paper Discussions are made based on its substantial elements The necessity of VHDL—AMS hardware description language in the application of analog/digital mixed signal IC’s and its advantages are explained through the description of its theoretical basis, principle of mixed modeling and its application scopes [WT5HZ]

Abstract: Interconnects now play a key role in high performance analog integrated circuits Partial Element Equivalent Circuit (PEEC) models for analyzing interconnects are usually simulated with numerical simulator In this study, symbolic analysis is proposed to simulate the equivalent circuits of PEEC, as well as components and devices An interactive program is developed, which makes verification and optimization of the analog circuit design easier and more efficiently

Abstract: A charge pump phase-locked loop(PLL) based on voltage-controlled delay line (VCDL) is presented, which is used to locate the sampling clock edge in the clock recovery circuit. This design is independent on environment and process. The improved delay unit in VCDL efficiently lowers the output jitter and a low-pass filter (LPF) is designed to avoid the charge-sharing error. Using 0 35 μm TSMC process, the circuit can operates at a low voltage of 3 3 V.In the worst-case condition, simulated jitter of single delay module is 20 ps and static phase error is only 45 ps between input and output.

Abstract: WT5”BZ]Current very large scale integration (VLSI) technology makes it possible to manufacture large area integrated circuits with sub micrometer feature sizes and integrate millions of elements into a single chip However, imperfections in the fabrication process result in yield reduction, especially for IC functional yield Models of the defect outline, the spatial distribution and the size distribution statistics are described in the paper Mechanisms of the IC functional yield loss are discussed in particular and the analysis model of the IC functional yield is introduced in detail [WT5HZ]

Abstract: WT5”BZ]Cell based ASIC design methodology makes cell layout generation tool essential CMOS cell layout generation consists of transistor placement, inner cell routing and layout compaction In this paper, based on different layout styles, the development of placement, routing and compaction algorithm is reviewed Several cell layout generators are described and problems associated are discussed [WT5HZ]

Abstract: WT5”BZ]The process of copper interconnections in ULSI and its development are described in this paper Furthermore, the key technologies, such as barrier selection, copper deposition and chemical mechanical polishing (CMP) are analyzed and discussed in detail [WT5HZ]

Abstract: A 32-bit RISC microprocessor is presented in the paper, which is compatible with Motorola's MCore product The processor structure and its specific units are described in detail Software simulation and hardware validation are made And synthesis results are summarized