Abstract: Intel has been continuously striving to provide environmentally green micro-electronic packaging solutions for high-density interconnect (HDI) product applications. The environmentally green initiative consisted of providing lead-free (Pb-free) packaging materials solutions as well the enabling of halogen-free (HF) substrates technology to eliminate the use of brominated flame retardants. This paper discusses the challenges overcome by Intel to deliver on both aspects of environmentally green packaging. Although Intel’s efforts to enable Pb-free and HF-compliant packaging solutions have been wide-ranging, the scope of this paper is limited to discussing the key technology development challenges faced in transitioning to Pb-free materials in first-level interconnects (FLI), second-level interconnects (2LI), solder thermal interface materials (STIM) applications, and halogen-free (HF) substrate materials. The transition to Pb-free micro-electronic packaging materials and HF substrate technology required a paradigm shift in the industry, needing extensive benchmarking initiatives and sharing cross-technology learnings across the industry and academia. The delivery of Pb-free packaging solutions across FLI, 2LI, and STIM applications as well as HF substrate technology has strongly reinforced Intel’s One Generation Ahead (OGA) philosophy in micro-electronic packaging.

Abstract: In the relentless pursuit of Moore’s Law, Intel’s Technology Development cycle results in a new semiconductor production process every two years. As this continuous cycle of new products moves from conception to market, so do the innovative environmental solutions designed to meet Intel’s philosophy of environmental excellence. Intel’s success in design-forenvironment (DFE) is widely recognized. In 2007 Intel was rated the top U.S. technology company to be named to the Dow Jones Sustainability Index—for the seventh straight year. In normal process technology development cycles, Intel’s environmental systems are developed in parallel with the semiconductor manufacturing process. However, Intel is a global company and this proactive process sometimes needs adjusting to accommodate unique differences in local conditions. Such a situation occurred recently for a new Intel HighVolume Manufacturing (HVM) facility that was under construction in an arid region. The technology development team faced a triple challenge of finding a technology solution that would meet water conservation needs, new environmental standards, and a compressed project schedule. The project site was being required to treat the entire wastewater stream of both new and existing factories to achieve a very high level of wastewater effluent quality and to meet water reuse and conservation priorities of the local authorities. Meeting the schedule while designing and implementing a system capable of achieving effluent quality targets that would also maximize water reuse became a paramount task, since the business permit for operating the Fab would not be issued without this infrastructure. With only half of the normal development time available and no prior Intel experience with the proposed wastewater treatment technology, a task force was formed from multiple business groups to achieve successful completion of the project. In this paper we focus on the following aspects of the aforementioned situation: 1. How the team incorporated risk-taking with other Intel best-known-methods to address both schedule and technology challenges. 2. The intensive technical study that resulted in the definition and optimization of the technology. 3. Value Engineering that resulted in design and construction of this system at costs normally associated with systems that are an order-ofmagnitude smaller. 4. Creating greater water recycle opportunities by treating wastewater to such high standards. 5. The additional benefits of being able to treat other waste streams that are currently segregated. 6. The future challenges and opportunities associated with completion of this project.

Abstract: The goal of the \" Green Building \" project is to reduce the impact of construction on the environment. By doing this Intel joins the world's efforts in sustainable construction. The Green Building project differs from conventional building projects by assigning equal priorities to economical, social, and environmental goals. The new Intel R&D building, located in Haifa, Israel, is designed per the Leadership in Energy & Environmental Design (LEED*) rating system. These were the objectives of the design process: • To achieve energy and water savings. • To incorporate environmental friendly materials into the building. • To implement waste and recycling policies. • To provide a high-quality internal environment. • To position and plan the site to reduce the impact on the environment. The new Intel R&D building is now under construction and is undergoing a certification process. Once awarded, it will become Intel's first certified Green Building worldwide! This project was initiated to address the need for a \" smart \" building. The Green Building concept was found to be the most suitable for this purpose, particularly for an R&D building. Research shows that such a building improves tenants' satisfaction and health, enabling higher employee productivity; and it reduces energy and maintenance costs for the owners. The estimated ROI due to operational costs is approximately five years. In this paper we show the innovation, logic, drivers, and triggers that helped us overcome significant challenges in dealing with an inexperienced local building industry, and in driving innovation in a large organization. Our engagement with the local construction industry adds a new dimension to the concept of Intel social responsibility. Our key message is that it is possible to execute a local and innovative initiative successfully, even in global corporations, once the initiative supports the corporate values.

Abstract: The ’64 Mustang is a classic: a car that people still talk and reminisce about 44 years on. Do you mess with success and change a winning formula? No, but you do update a design to fix weaknesses in the original (better audio, air-conditioning, reliability, etc.) and to address new consumer desires as the market changes (efficient engines to address fuel economy, catalytic converters to address the need for a cleaner environment, etc.). The Universal Serial Bus (USB) is a classic of the computer world. It was introduced in 1996 and is now a ubiquitous computer interface. When it was developed in the mid ‘90s it was targeted for mainstream computers of the time, optimized primarily for consumer ease of use and low device cost. Around 2002, USB 2.0 was introduced offering a performance bump to 480 Mbps; again optimized to meet similar criteria. Although many characteristics of the USB are top-notch, its impact on platform power consumption has been downright abysmal. While power consumption was not an important criterion of its original design, the USB has become a defacto feature for battery-powered platforms where low power is key. In addition, global concerns over energy consumption and carbon emissions have made energy efficiency an important market requirement even for desktop and server systems [1]. Therefore, like the classic Mustang, it’s time to overhaul the USB in a manner that preserves the goodness which has helped make it such a successful interconnect. In this paper we first outline the USB power issues and look at their impact on mobile platforms. We then discuss ways of resolving these issues. Although the focus here is clearly on notebook systems, most issues and solutions apply to other systems as well. INTRODUCTION To comprehend USB’s power problems you first need to have a basic understanding of how it works. We won’t try and make you an expert on USB architecture; rather, we will just provide enough detail so you can understand the fundamental problems and how the proposed fixes address these. The root of most of the power issues is the fact that the USB is based on an architecture that constantly polls devices. Although this creates a simple and low-cost device model, it is fundamentally inefficient—especially when the device is idle or has little data to transfer. Specifically, a USB device is incapable of transferring data or generating an interrupt without being polled by the host. The best it can do is indicate the rate at which it wants to be polled in the event that activity occurs. This rate is typically assigned statically when the device is first configured and tuned for highly active phases (e.g., to maximize throughput). We will go into a little more detail about how a USB device is designed to work in this polled environment and then discuss why polling creates power problems. Figure 1 illustrates the behavior of normal (non-polled) data transfers for PCI devices. In this bus model, devices are generally implemented as fully capable bus masters. When a PCI device needs to transfer data it simply requests control of the bus and initiates one or more cycles to main memory (green line #1), which also results in a snoop cycle to the CPU (green line #2) to ensure data consistency in case the memory contents reside in the CPU cache. Contrast this to the USB model where the device must wait until the next time it is polled by the host to transfer data, or more importantly, the host must continually poll a device just to see if it has data to transfer. The USB Intel Technology Journal, Volume 12, Issue 1, 2008 Making USB a More Energy-Efficient Interconnect 18 provides two general models for data transfers: synchronous and asynchronous. Synchronous transfers are polled at a guaranteed periodic rate with a maximum frequency of once every microframe (125 microseconds). This corresponds to the Isochronous and Interrupt endpoint types. Conversely, asynchronous transfers are not polled at a guaranteed rate, but for most implementations this occurs quite frequently (many times per microframe) to achieve high data throughput when needed. Bulk and Control endpoints belong to this transfer type.

Abstract: In this paper we examine the challenges of increasing data center power consumption and higher energy costs in the face of ever-increasing computing needs. An examination of how power is allocated to computing resources in data centers shows that current methods do not result in optimal use of available data center power and space. We identify requirements that server platforms must address to solve data center power problems, and we offer a solution that includes a platform resident Policy Manager (PM). The PM monitors power and thermal sensors and enforces platform power and thermal policies. We explain how the PM can be used as the basis of a data center power management solution. We present results from a Proof of Concept (PoC) implementation, and we conclude by showing that a policy-based approach is powerful for maximizing power allocation within a given power envelope and increasing server density in data centers. INTRODUCTION One of the biggest challenges for data center operators today is the increasing cost of power and cooling as a portion of the total cost of operations. As shown in Figure 1, over the past decade, the cost of power and cooling has increased 400%, and these costs are expected to continue to rise. In some cases, power costs account for 40-50% of the total data center operation budget. To make matters worse, there is still a need to deploy more servers to support new business solutions (Figure 2). Data centers are therefore faced with the twin problem of how to deploy new services in the face of rising power and cooling costs. In a recent survey of data centers (Figure 3), 59% identify power and cooling as the key factors limiting server deployment. If these trends continue, the ability of data centers to deploy new services will be severely constrained. To overcome this constraint, data centers have three choices: expand power and cooling capacity, build new data centers, or employ a power management solution that maximizes the usage of existing capacity. The first two choices can be very expensive because they involve capital expenditure for purchasing and installing expensive new power delivery equipment. For this reason, the power management approach bears close examination, and this approach is the focus of the rest of our paper. For previous work in this area, the reader is referred to Felter et al. [4] who examine the benefits of dynamic power budget allocation, Femal [5] who examines the benefits of monitoring and coordinating power distribution to achieve higher application throughput, [6] where a framework to monitor power is discussed, and Bianchini [7] who presents a survey of energy management techniques by type of server system. Intel Technology Journal, Volume 12, Issue 1, 2008 Dynamic Data Center Power Management: Trends, Issues, and Solutions 60 Figure 1: IDC Report of data center cost structure and trend Figure 2: Expected growth in server count Figure 3: Factors limiting server growth Our paper is organized as follows. In the next section we describe the current data center power allocation approach and the resulting problems; we follow this by proposing a new method for dealing with data center power allocation and describe the resulting server requirements; we then describe the role and functions of a platform resident Policy Manager (PM) and show how it addresses these requirements. Finally, we present the results of a PM Proof of Concept (PoC) and the benefits it offers data centers. CURRENT POWER ALLOCATION METHODS A typical data center power distribution hierarchy is designed to deliver a fixed amount of power to the room and then to each rack. The challenge of the data center operator is to determine the number of servers for each rack while ensuring that the overall rack (hence room) power consumption does not exceed the limit. To do this, the operator must make certain assumptions about the maximum power consumption per server. For most data centers, there are two ways of determining this: 1) using server nameplate power value, and 2) using a derated nameplate value. The server nameplate value, which is marked on the server by the manufacturer, is the maximum possible power value that the server can consume. Actual power consumption is typically much less that the nameplate power. Most data center operators are aware that typical server power consumption never reaches the nameplate value, and one way for them to increase server density is to derate the nameplate power by a certain percentage— depending on the workload that is deployed on the server. Change in Server Requirements