Abstract: The mobile thin and light platform has a limited cooling capability, in part due to a form factor that limits the volume available for the thermal solution. The high performance of the Pentium M processor on 90nm process technology and the Intel 915 Chipset in the second-generation platform built on Intel Centrino mobile technology demands a high electrical power and generates substantial heat, presenting a challenge to the thin and light notebook system designer. In this paper, we addresses two methods of dealing with the thermal challenge. First, we discuss the path-finding effort to improve the thermal interface materials (TIMs) that allow a good thermal contact between processor and thermal solution, minimizing the transistor temperature of the bare-die Pentium M processors. Two tester methodologies are described, and the need to test TIMs under mobile usage conditions is emphasized. We also discuss the reliability test methodology for TIMs with a focus on the effect of mobile usage conditions affecting long-term reliability of the TIM. ® Pentium is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. ® Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. TM Centrino is a trademark of Intel Corporation or its subsidiaries in the United States and other countries. We then focus on power-based thermal state estimation as a platform thermal management technique. This technique is used to detect and limit the thermal impact of power virus workloads. In the second-generation platforms built on Intel Centrino mobile technology, the Intel 915 Chipset Graphics and Memory Controller Hub (GMCH) is uniquely positioned to understand much of the workload for the platform. The Intel 915 GMCH has implemented filter-based thermal management. Several key usage models for filter-based thermal management are explored in detail: detecting and limiting the impact of power viruses on system memory and detecting and limiting the impact of power viruses on chipset memory controller hubs. INTRODUCTION Notebook system designs vary significantly from designer to designer; however, they are all densely packed with components and devices, which leave the system with little room for cooling. The problem is compounded by the limited room inside a thin and light notebook product, which typically has a one-inch total thickness when folded and a 17 mm inner vertical space in the lower half of the notebook computer. Figure 1 shows a schematic electrical layout of the major components in the second-generation 1 A power virus is an unusually intensive workload that maximizes power consumption. Most useful applications draw only a fraction of the power a power virus consumes. Intel Technology Journal, Volume 9, Issue 1, 2005 Interface Material Selection and a Thermal Management Technique 76 platforms built on Intel Centrino mobile technology. Figure 2 shows a layout of platform-based notebook system that is roughly representative of performance thin and light notebook designs in the industry. In general, the low-profile thin and light form factor limits the flexibility of thermal solution choices for the system components that must be cooled in order to get any appreciable performance. Figure 1: Electrical schematic of the secondgeneration platforms built on Intel Centrino mobile technology Figure 3 shows the use of the remote heat exchange, the predominant method of cooling of high-power components that require dedicated active cooling. In remote heat exchange, the thermal energy is transported to a location, typically via a heat pipe, where a larger fan and heat exchanger can be used. Also shown in Figure 3 are the silicon portion of the hot component (bare die assumed), the attached hardware for coupling the thermal solution to the hot component, and the key temperature monitor points typically used to characterize the performance of the solution. In the first section, we discuss the ability to transfer the thermal energy from the processor to the thermal solution by using thermal interface materials (TIMs). Figure 2: Layout of typical thin and light notebook (base only with top surface removed)

Abstract: The microelectronic industry has continuously driven for greater integration of functionality and capability. This has led to some significant challenges for the industry. For example, to improve electrical performance, materials with low dielectric constants are being added to the silicon structures. These fragile materials in silicon interconnect layers present a significant challenge to the development of reliable package assembly processes. Similarly, the introduction of new features has led to the need for smaller, weaker interconnects between the package and the system board. Recently, these trends have been coupled with changes to the operating environment for electronic devices. With the growing trend toward mobile computing, the risk of interconnect damage from devices being dropped has grown. This is further complicated by the legal requirement to remove lead-containing materials from the package. This requirement affects the package interconnects by eliminating solder materials that have been traditionally used, whose behavior is well understood and quantified. The traditional approach to resolving such challenges involves finding solutions through large designed experiments to optimize the design, material, and process choices. These methods have met with difficulty due to the complexity and interdependency of the issues. In this paper we look at the application of new engineering mechanics tools and methods to better understand the fundamentals of package reliability. To determine the reliability, one must be able to assess both sides of the reliability equation: the stress imposed by the loading condition and the material strength. In general, if the strength of the interconnect exceeds the stress applied throughout the life of the package, then it will be reliable. While it is not always possible to accurately predict and quantify both sides, the techniques discussed can help engineers make better judgments and can provide direction to technology development. In this paper we describe three case studies using the approach described above. The first case study describes how bump pull/shear metrologies are used to understand the impact of various assembly and silicon fabrication processes on the silicon interconnect strength. The second case study provides a thorough analysis of second-level interconnect reliability (BGA) under shock loading conditions in laptops. The last case study shows how these measures can be used to enhance the material selection process in selecting a second-generation lead-free solder material. This approach has lead to the successful launch of lead-free package technologies with higher density interconnects.

Abstract: As next-generation package technologies become more complex, the isolation of defects and their failure analysis has became more challenging. The complexity of newgeneration packages, driven by Moore’s Law, include a greater number of components allocated to smaller form factors, thus creating defects that are difficult to isolate and characterize, such as metal migration, dendrite growth, microcracks, wirebond microfractures, plane-toplane shorting, high-resistance, defects in multistacked dice, via delamination, and bump bridging. A continued effort has been made to close these technical gaps in analytical tools and techniques. By guiding and codeveloping next-generation analytical tools, we have been able to successfully identify failure modes and root causes to rapidly advance unique and new solutions at Intel in current package technologies. In this paper we discuss how these tools are being used in the failure analysis flow, as well as the technical gaps that have to be addressed in order to meet the fault isolation and failure analysis challenges of next-generation package technologies.

Abstract: As one of the founding members of the RosettaNet consortium, Intel has aggressively pursued utilizing RosettaNet to support its supply chain. Over the past five years, Intel has implemented over 1000 Trading Entity (TE) touch points, encompassing 24 different RosettaNet Partner Interface Processes (PIPs*) enabling more than 50 unique business transactions with over 200 TEs. In 2004 alone, Intel realized nearly $40M ROI in business value. We begin with an overview of key RosettaNet technical components. We then summarize the success Intel had over the past years in building new business processes and the e-Business infrastructure of RosettaNet. Finally, we explore the future of Business-to-Business (B2B) exchanges and the next generation of B2B architecture.

Abstract: Semiconductor manufacturing is a very capital-intensive endeavor that can return substantial revenues. The production planning process must deliver a build schedule that makes efficient use of Intel’s capital resources while satisfying as much demand as possible. This schedule should comprehend the flexibility of production resources, the dynamic nature of supply and demand within Intel’s supply chain, as well as the timing of new product releases and production facility improvements. Previous planning processes relied on spreadsheets for heuristic manual decision making with localized data. With the growing complexity of Intel’s products and manufacturing processes, these methods had become inadequate and unsustainable. Upgrading the planning process required better decision algorithms, improved data management, as well as more automated and integrated planning processes. New tools based on Mathematical Programming were implemented in multiple divisions and stages of Intel’s supply chain. The development team worked closely with the users to understand their business and capture their operating logic to create automated decision systems. These tools balance requirements to satisfy demand, achieve inventory targets, and remain within production capacity to reduce costs and satisfy demand across Intel’s supply chain. They have been developed to evolve the planning process while maintaining visibility to the logic and data flow to facilitate continuous improvement. Advances in data management were required to complement decision algorithm improvements. The new tools integrate directly into source data systems while providing planningand optimization-specific functionality, including mechanisms to track parameter changes and supply dynamic reporting capabilities. These advances allow planners to more easily identify data issues and to better understand the planning recommendations from the tools. The robust data management infrastructure enables tighter integration of organizations, increased scalability, and more consistent implementation of solutions across business units. Advances in decision algorithms, data management, and system automation led to improvements in solution quality, data health, and productivity. The new applications allow planners to rapidly perform analyses on multiple business scenarios to produce better solutions and improve collaboration with other organizations. While results reported by the business users over the past four years have proven the stability and value of this decision support technology, there is still work to be done. Plans for extensions and continuous improvement are provided in the last section of this paper.

Abstract: The PCI Express architecture, both as a unified foundation of I/O, graphics, and networking interconnections, and as a preeminent building block on chip-to-chip, board-to-board, and system-to-system, is widely adopted by multiple market segments in the computing and communication industries. PCI Express architecture is a state-of-the-art serial interconnect technology that keeps pace with recent advances in processor and memory subsystems. From its initial release at 0.8 V, 2.5 GHz, the PCI Express technology has evolved to the general-purpose interconnect of choice for a wide range of applications, including graphics, storage, networking, etc. The PCI Express architecture retains the familiar PCI software and configuration interfaces for seamless migration and adoption in desktop and mobile PC platforms, enterprise servers and workstations, and, increasingly, a wide range of communication and embedded systems. The PCI Express technology addresses requirements from multiple market segments in the computing and communication industries, and it supports chip-to-chip, board-to-board, and adapter solutions at an equivalent or lower cost than existing PCI designs. Currently, PCI Express architecture supports a 2.5 GT/s signaling rate that yields 500 MB/s bandwidth per lane and a maximum bandwidth of 16 GB/s in a 32-lane configuration. Consistent with the expected cadence of I/O performance progression, the next generation of the PCI Express ∗ Other brands and names are the property of their respective owners. interconnect will support a signaling rate of 5 GT/s, doubling the performance of the existing links. The PCI Express interconnect provides numerous architectural improvements over existing I/O technologies. It defines a native hot-plug scheme, enables aggressive power management, provides advanced Reliability, Availability, and Serviceability (RAS) and Quality of Service (QoS) features, and simplifies PCB layouts. In this paper, we discuss the unique, universal capabilities and values of PCI Express technology emerging in the next generation of mobile platforms. We focus on PCI Express architecture, power management, and mobile applications such as graphics, networking, and form factors including the ExpressCard module as well as future form factors such as the PCI Express Wireless Card and the PCI Express Mini Card. Finally, we cover the next generation of mobile PC platforms built on the Intel Centrino mobile technology.

Abstract: This paper considers two major enhancements to Intel’s graphics memory controller hubs, as embodied in the Intel 915 Express Chipset Family. First, we discuss the microarchitecture of the 3D pipeline and the steps taken to optimize it for peak performance. Secondly, we present the TV output feature, which is important for merging the personal computer and the television into a single platform, in support of Intel’s digital home initiative. In the 3D graphics section, we present an overview of the microarchitecture in the context of the design challenges inherent in a next-generation integrated graphics accelerator. This section demonstrates the key roll benchmark analysis played in optimizing the performance of various components of the graphics pipeline such as command processing, primitive processing, pixel shader floating point units (FPUs), caching algorithms, etc. Obtaining a balanced pipeline is central to achieving maximum performance. With the merging of the personal computer and the television into a single platform for the digital home, new requirements are emerging for the standard home PC. High among these features is the inclusion of the television output interface or the digital television encoder. Television signals are quite different from the ® Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. standard computer monitor connections and therefore have very different requirements. The TV output function also needs to be highly flexible because television encoding algorithms are different depending on the country of origin. 3D MICROARCHITECTURE INTRODUCTION Significant feature and performance enhancements have been incorporated into Intel’s third-generation graphics processing unit. The performance of these platforms generally exceeds expectations, with the Intel 915 Express Chipset Family demonstrating approximately 2.4 times the performance of its predecessor, as measured using Future Mark’s 3DMark 2001 [1] benchmark, and approximately 10 times the performance using the 2003 version of their benchmark [2]. This paper presents the key architectural challenges associated with attaining these performance levels; we intend that our methodologies and conclusions will provide valuable insight for other design projects. A cursory understanding of the state of the personal computer graphics industry is necessary to appreciate the task presented to the graphics team. ∗ Other brands and names are the property of their

Abstract: Microelectronic packages continue to undergo significant changes to keep pace with the demands of high- performance silicon. From the traditional role of space transformation and mechanical protection, packages have evolved to be a means to cost-effectively manage the increasing demands of power delivery, signal distribution, and heat removal. In the last decade or so, increasing frequency and power levels coupled with lower product costs have been driving new package technologies. Some examples of this are the migration from wirebond to flip chip interconnect and ceramic to organic package substrates. Recently, architectural changes like the introduction of multicore processors, material changes such as the low-K dielectrics on the silicon, and lead-free second-level interconnects have introduced a new set of challenges that require innovative package technology solutions. As we look forward, increased levels of current, increased power density, and high-bandwidth signaling are expected to create challenges in all disciplines within the package field. In addition to these technical challenges, market forces such as declining computer prices, increased user experience through miniaturized devices, wireless connectivity, and longer battery life would make these challenges even more complex. In this paper we provide an overview of trends and challenges in the areas of power delivery, signal transfer, thermal management, miniaturization, and wireless package technologies. We also examine some of the potential solutions that are being developed to meet these challenges.