TL;DR: This paper presents an overview of hardware implementations for the two commonly used types of public key cryptography, i.e. RSA and elliptic curve cryptography, both based on modular arithmetic.

TL;DR: Different techniques to reduce the power consumption in low-voltage fast-settling operational amplifiers for switched-capacitor applications are discussed, including the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters.

TL;DR: The method is demonstrated through the design of a circuit for conversion of quaternary inputs into the corresponding binary bits in a standard 1.5 µm digital CMOS technology.

TL;DR: The new one-dimensional structure proposed in this paper has been extended to a separable two-dimensional stack filter and has a better performance in terms of area and time delay.

TL;DR: The current paper presents a new AB2 algorithm based on the MSB-first scheme using a standard basis representation of Galois fields, GF( 2m), and parallel-in parallel-out and serial-in serial-out systolic realizations for computing AB2 and inversion/division in GF(2m).

TL;DR: A hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as the goal and uses heuristic approach to decompose the problem of minimum delay Steiner Tree into hierarchy and construct the sub-trees based on dynamic programming technique.

TL;DR: A CMOS operational amplifier with input/output rail-to-rail range with dynamically biased input level shifters, controlled by a novel tuning scheme, to extend the input common-mode voltage range from one rail to the other is presented.

TL;DR: It is shown that the problem of clustering a combinational circuit under the area or pin constraint so that the clusters are disjoint and the overall input/output delay is minimized is computationally intractable.

TL;DR: A new 5-modulus set is presented, that expands the dynamic range in comparison with the popular 3-moduli sets, and expresses the multiplicative inverse of each modulus in a compact form that eases the conversion.

TL;DR: Since DCT/IDCT core needs matrix transposition, this work proposes an orthogonal transpose memory scheme that satisfies horizontal and vertical signal transfer and shows superior performance for the parallel processing compared with the ROM-based distributed arithmetic architecture andROM-based parallel multiplication.

TL;DR: A floating voltage hold circuit is proposed which enables the accurate addition of signal voltages without requiring precision components and is well below those previously reported for 1.5-bit stage algorithmic ADCs.

TL;DR: It is shown that the ratio of the number of gates of Ci in SPP over SOP decreases exponentially with i, being very small even for small values of i (ratio > 0.2 for i = 9).

TL;DR: The extension of the scope of Integration—the VLSI journal to cover the analog and mixed-signal field was a natural evolution and hopefully, this Special Issue inaugurates a permanent presence of papers on analog and Mixed-Signal design.

TL;DR: The design and implementation of FPGA-based configurable FSK demodulator, which can support multi-standards such as ITU-T V.23 and BELL 202, is presented.

TL;DR: A new approach has been taken to restructure the adaptive decimation algorithm to a form that includes only small amount of arithmetic operations, which can be implemented with simple logic circuits and practically free from complicated numerical computation.

TL;DR: The problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams based on DDDs with the minimum number of vertices can be formulated as that of multi-level multi-way hyper graph partitioning with balance constraints and solved in two phases by connectivity-oriented initial clustering and iterative improvement.

TL;DR: This paper proposes several low-power synthesis techniques for VLSI implementation of DSP systems both at the algorithmic and architectural levels and reports that up to 80% in the overall implementation of Viterbi decoder and in the implementation of folded FIR filters saving in power consumption has been reported.

TL;DR: This work generates verification patterns with 100% coverage of a sub-class of POF, called 2-POF, and provides theoretical arguments and experimental results backing the efficiency of these patterns also for detecting higher-order POFs.

TL;DR: This paper presents a CMOS 0.8 µm mixed-signal half-duplex Modem ASIC for data transmission on the low-voltage power line, which includes all the analog circuitry needed for input interfacing and modulation/ demodulation.

TL;DR: Techniques for simplifying the process of fuzzification and defuzzification and its subsequent effect of reducing system and computational complexity are discussed.

TL;DR: An improved circuit-partitioning algorithm MCER, based on a min-cut equivalence relation, which not only inherits to take advantage of flow theory, but also incorporates a subsets movement-based method to utilize internal equivalent topological structure of circuit.

TL;DR: A method for efficiently generating representative input vectors for large parametric combinational designs is presented, based on an exhaustive simulation of a small design and a conversion of the representative input vector of the small design to the large input length.

TL;DR: A voltage adapter pad circuit is presented, the circuit is oriented to applications where multiple digital units working at different voltage levels communicate in a bus connection.

TL;DR: Analysis shows that the low-voltage D-latch topology does not necessarily allow for a power saving or a better power efficiency, and applications where this topology exhibits some advantage over the traditional implementation are identified.