Abstract: An algorithm for the analysis of multivariate data is presented and is discussed in terms of specific examples. The algorithm seeks to find one-and two-dimensional linear projections of multivariate data that are relatively highly revealing.

Abstract: Piecewise approximation is described as a way of feature extraction, data compaction, and noise filtering of boundaries of regions of pictures and waveforms. A new fast algorithm is proposed which allows for a variable number of segments. After an arbitrary initial choice, segments are split or merged in order to drive the error norm under a prespecified bound. Results of computer experiments with cell outlines and electrocardiograms are reported.

Abstract: Preparata, Metze, and Chien [1] gave necessary conditions for identification of all faulty units in a system S capable of automatic fault diagnosis. We show that these conditions are sufficient if in S no two units test each other. Necessary and sufficient conditions are also obtained for the general case when no such restriction is placed on S.

Abstract: The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware configurations are examined for cost, speed, and complexity tradeoffs. A new, especially attractive FFT computer architecture is presented as an example of the utility of this technique. Compensated and modified CORDIC algorithms are also developed.

Abstract: An algorithm for the analysis of multivariate data is presented and is discussed in terms of specific examples. The algorithm seeks to find one-and two-dimensional linear projections of multivariate data that are relatively highly revealing.

Abstract: The commonly used stuck-at fault fails to model logic circuit shorts. Bridging faults are defined to model these circuit mal-functions. This model is based on wired logic which is a characteristic of many logic families such as resistor-transistor logic (RTL), diode transistor logic (DTL), emitter-coupled logic (ECL), etc. It does not apply to TTL circuits. The model also limits to fan-out-free leads.

Abstract: The work of software cost forecasting falls into two parts. First we make what we call structural forecasts, and then we calculate the absolute dollar-volume forecasts. Structural forecasts describe the technology and function of a software project, but not its size. We allocate resources (costs) over the project's life cycle from the structural forecasts. Judgment, technical knowledge, and econometric research should combine in making the structural forecasts. A methodology based on a 25 X 7 structural forecast matrix that has been used by TRW with good results over the past few years is presented in this paper. With the structural forecast in hand, we go on to calculate the absolute dollar-volume forecasts. The general logic followed in "absolute" cost estimating can be based on either a mental process or an explicit algorithm. A cost estimating algorithm is presented and five tradition methods of software cost forecasting are described: top-down estimating, similarities and differences estimating, ratio estimating, standards estimating, and bottom-up estimating. All forecasting methods suffer from the need for a valid cost data base for many estimating situations. Software information elements that experience has shown to be useful in establishing such a data base are given in the body of the paper. Major pricing pitfalls are identified. Two case studies are presented that illustrate the software cost forecasting methodology and historical results. Topics for further work and study are suggested.

Abstract: A discrete cosine transform (DCT) is defined and an algorithm to compute it using the fast Fourier transform is developed. It is shown that the discrete cosine transform can be used in the area of digital processing for the purposes of pattern recognition and Wiener filtering. Its performance is compared with that of a class of orthogonal transforms and is found to compare closely to that of the Karhunen-Loève transform, which is known to be optimal. The performances of the Karhunen-Loève and discrete cosine transforms are also found to compare closely with respect to the rate-distortion criterion.

Abstract: Threshold selection for picture segmentation is relatively easy when the frequency distribution of gray levels in the picture is strongly bimodal, with the two peaks comparable insize and separated by a deep valley. This report describes a method of handling cases in which the peaks are very unequal in size and the valley is broad. A Laplacian operation is applied to the picture to determine points that lie on or near the edges of objects. Threshold selection becomes easier when the frequency distribution of gray levels of these points is used.

Abstract: This paper shows that there exists a class of functions called data manipulating functions (DMF's), in sequential as well as paralel processors. The circuits used to achieve these functions can be considered to form an independent functional block, called a data manipulator. A basic organization applicable to both sequential and parallel processors is then suggested. The main deviation of a parallel processor orgaization from the conventional Von Neumann organization is seen to be in the bit-slice (bis) manipulating functions. A comprehensive set of bis manipulating functions from the categories of permuting, replicating, spacing and masking is given. Implementation of the last category, the masking functions, is usually through a mask register by defining its content (mask pattern). It is found that for many operations the required mask patterns are periodic and/or monotonic. The upper bounds of generating these patterns are found. The techniques and designs of two data manipulators for the first three categories of DMF's (permuting, replicating, spacing) are given. Periodic and monotonic mask patterns are also used to help in implementing some of these functions. In addition, it is shown that the data manipulator designs presented in this paper are extremely flexible to suit the requirements of various parallel processors.

Abstract: An algorithm is derived for multiprobe testing for shorts, opens, and wiring errors in any multiterminal wiring network, such as a printed circuit board, wiring harness, multiconductor cable, or backplane wiring board. For behavioral testing the minimum number of tests required, always achievable, is equal to p - 1 + [log 2 q], where p is the number of terminals in the largest interconnected cluster in the network, and q is the total number of clusters, including isolated terminals. For structural testing the number of tests required is less, and can be as small as [log 2 q] + 1 depending upon the assumptions made regarding the types of faults that can occur.

Abstract: The effectiveness of various forms of contextual information in a postprocessing system for detection and correction of errors in words is examined. Various algorithms utilizing context are considered, from a dictionary algorithm which has available the maximum amount of information, to a set of contextual algorithms utilizing positional binary n-gram statistics. The latter information differs from the usual n-gram letter statistics in that the probabilities are position-dependent and each is quantized to 1 or 0, depending upon whether or not it is nonzero. This type of information is extremely compact and the computation for error correction is orders of magnitude less than that required by the dictionary algorithm.

Abstract: The use of a gray level transformation which transforms a given empirical distribution function of gray level values in an image into a uniform distribution has been used as an image enhancement as well as for a normalization procedure. This transformation produces a discrete variable whose empirical distribution might be expected to be approximately uniform since it is related to the well known distribution transformation. In this correspondence, an extension of the theorem is given which shows that the theorem "almost" holds for an "almost" continuous input distribution. The application of the discrete distribution transformation to computer image enhancement is considered.

Abstract: Two simple heuristic algorithms for piecewise-linear approximation of functions of one variable are described. Both use a limit on the absolute value of error and strive to minimize the number of approximating segnents subject to the error limit. The first algorithm is faster and gives satisfactory results for sufficiently smooth functions. The second algorithm is not as fast but gives better approximations for less well-behaved functions. The two algorithms are ilustrated by several examples.

Abstract: Recursive restoration of two-dimensional noisy images gives dimensionality problems leading to large storage and computation time requirements on a digital computer This paper shows a two-dimensional second-order Markov process representation can be used for fast recursive restoration of images with small storage requirements Advantages of this method over existing techniques are illustrated by means of examples

Abstract: A high-level language, SIMPL (Single Identity MicroProgramming), for horizontal microprogramming has been developed. This language allows the SIMPL compiler to easily detect concurrent microoperations and to optimize their intricate timing and concurrency for generating highly parallel and efficient object microprograms in horizontal formats. This unique feature accrues from the single assignment concept for multiprocessing languages that was adapted to the design of SIMPL.

Abstract: There are several instances where the classical method of triple-modular redundancy (TMR) reliability modeling may provide predictions which are inadequate. It is shown that for even simple networks such as those exhibiting fan-in and fan-out, classical methods may predict a reliability that is higher than or lower than the actual reliability. Furthermore, the classical method gives no hint as to whether the predicted number is high or low. As a solution to this problem, a method of partitioning an arbitrary network into cells such that faults in a cell are independent of faults in other cells is proposed. An algorithm is then given to calculate the reliability of any such cell, by considering only the structure of the interconnections within the cells. The value of the reliability found is exact if TMR is assumed to be a coherent system. An approximation to the algorithm is also described; this can be used to find a lower bound to the reliability without extensive calculation.

Abstract: An important measure concerning the use of statistical decision schemes is the error probability associated with the decision rule. Several methods giving bounds on the error probability are presently available, but, most often, the bounds are loose. Those methods generally make use of so-cailed distances between statistical distributions. In this paper a new distance is proposed which permits tighter bounds to be set on the error probability of the Bayesian decision rule and which is shown to be closely related to several certainty or separability measures. Among these are the nearest neighbor error rate and the average conditional quadratic entropy of Vajda. Moreover, our distance bears much resemblance to the information theoretic concept of equivocation. This relationship is discussed. Comparison is made between the bounds on the Bayes risk obtained with the Bhattacharyya coefficient, the equivocation, and the new measure which we have named the Bayesian distance.

Abstract: Totally self-checking checkers for k-out-of-(2k + 1), (k + 1)-out-of-(2k + 1), and k-out-of-2k codes are given. The new checkers for the k-out-of-2k codes require only 2k tests to detect all stuck-at faults.

Abstract: Intermittent faults are those faults whose effects on the behavior of a system are present only part of the time. A probabilistic model for intermittent faults in digital circuits is suggested. A procedure for the detection of such faults in combinational circuits is proposed. The procedure employs the repeated application of tests that test for these faults as if their effects were permanent. The procedure is analogous to a sequential statistical decision problem. Least upper bounds on the number of repetitions of tests that detect a particular fault are derived. These bounds are then employed in designing optimum detection experiments. Such an optimization problem is found to be equivalent to an integer programming problem.

Abstract: This paper considers the use of control logic to reduce the number of tests required by a logic network and to simplify test generation. The properties of EXCLUSIVE-OR (EOR) circuits as control elements are examined. Systematic procedures are presented for modifying any combinational or sequential network so that the resulting network requires only five tests. These tests can easily be generated using a set of predefined test patterns of length five. The design of diagnosable networks using a limited amount of control logic is also discussed.

Abstract: An investigation of the various cache schemes that are practical for a minicomputer has been found to provide considerable insight into cache organization. Simulations are used to obtain data on the performance and sensitivity of organizational parameters of various writeback and lookahead schemes. Hardware considerations in the construction of the actual cache-minicomputer are also noted and a simple cost/performance analysis is presented.

Abstract: The presence of redundancy in combinational networks increases the cardinality of the test set to detect all stuck-at-faults. A solution to this problem is to identify and remove all redundancies in the networks before deriving test sets. It is shown in this paper that the identification of redundancy in arbitrary combinational networks is an extremely tedious problem.

Abstract: This paper considers a solution to the multiprocessor scheduling problem for the case where the ordering relation between tasks can be represented as a tree. Assume that we have n identical processors, and a number of tasks to perform. Each task T i requires an amount of time μ i to complete, 0 i ≤ k, so that k is an upper bound on task time. Tasks are indivisible, so that a processor once assigned must remain assigned until the task completes (no preemption). Then the "longest path" scheduling method is almost-optimal in the following sense.

Abstract: The arithmetic error detecting and correcting capabilities of product (AN) codes in residue number systems (RNS) are described. The redundancy necessary and sufficient to allow single residue digit error detection or correction is determined, under the hypothesis that the error affects either an arbitrary legitimate number or a number in overflow. It is shown that single-bit errors are also correctable, provided that the residue digits are conveniently encoded. Two different approaches to this problem are discussed. Simple procedures for error detection and correction are presented, and it is shown that the additive overflow detection is a by-product of such procedures. Proofs and examples are given.

Abstract: Most work on diagnosis of digital circuits has concentrated on the model of stuck-type faults. Although these faults are probably the most important class of faults, other types of faults do occur in practice and the occurrence of these other faults may affect the diagnosis of stuck-type faults. In this correspondence we consider the problems associated with detection of two other fault models, shorted diode and input Bridge faults, both corresponding to shorts. We present procedures for generating tests for stuck-type faults which also detect these other faults if they are detectable. Unlike stuck-type faults, the presence of undetectable short-circuit faults does not imply that the circuit can be simplified by removing inputs or gates. Undetectability of short-type faults corresponds to the ability to move fan-out points from an input to an output of a gate without changing the function realized by the circuit. Elimination of this type of redundancy does not necessarily lead to a simplified circuit.

Abstract: This paper describes an algorithm for the synthesis of applications-oriented microcode for a dynamically microprogrammable computer. The synthesis algorithm provides an iterative method for generating specialized architectures. Current attempts at generating specialized architectures can be considered as manual tuning due to human generation of specialized microcode. Heuristic instruction synthesis is described as one phase of a heuristic tuning process which attempts to automate the manual tuning process.

Abstract: This paper presents a new computerized technique to aid the designers of pattern classifiers when the measurement variables are discrete and the values form a simple nominal scale (no inherent metric). A theory of "prime events" which applies to patterns with measurements of this type is presented. A procedure for applying the theory of "prime events" and an analysis of the "prime event estimates" is given. To manifest additional characteristics of this technique, an example optical character recognition (OCR) application is discussed.

Abstract: A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. The results indicate that the deductive technique requires less CPU time for "loosely sequential" circuits or circuits having large numbers of simulated faults (e.g., >1000). The parallel technique is faster for small (e.g., <500 gates) "highly sequential" circuits or for small numbers of simulated faults. The storage required for a parallel simulator, however, can always be less than that required for a deductive simulator. In general, if sufficient memory is available, the deductive simulator is the more cost-effective simulator when a wide range of circuits is to be simulated and only one type of simulator is available. A substantial savings in logic circuit development cost can be realized when the proper simulation technique is used for logic design verification, fault analysis, and the generation of diagnostic data.