Abstract: High-voltage vertical Ga2O3 MISFETs are developed employing halide vapor phase epitaxial (HVPE) layers on bulk Ga2O3 (001) substrates. The low charge concentration of ~1016 cm−3 in the n-drift region allows three terminal breakdown voltages to reach up to 1057 V without field plates. The devices operate in the enhancement mode (E-mode) with a threshold voltage of ~1.2–2.2 V, a current ON/OFF ratio of ~108, an ON resistance of ~13–18 $\text{m}\Omega {}\cdot \text{cm}^{2}$ , and an output current of >300 A/cm2. This is the first report of high-voltage vertical Ga2O3 transistors with E-mode operation, a significant milestone toward realizing Ga2O3 based power electronics.

Abstract: We report enhancement-mode $\beta $ -Ga2O3 (BGO) MOSFETs on a Si-doped homoepitaxial channel grown by molecular beam epitaxy. A gate recess process is used to partially remove the epitaxial channel under the 1- $\mu \text{m}$ gated region to fully deplete at ${V}_{\textsf {GS}}= 0$ V. BGO MOSFETs achieve drain current density near 40 mA/mm and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio ~109 which is the highest reported for homoepitaxial normally-off BGO transistors. At ${V}_{\textsf {GS}}= \textsf {0}$ V, a breakdown voltage of 198 and 505 V is achieved with the source–drain spacing of 3 and $8~\mu \text{m}$ , respectively. The power switching figure of merits for dc conduction and dynamic switch losses meet or exceed the theoretical silicon limit and previously reported depletion-mode BGO transistors.

Abstract: A 400-nm thick composite field plate oxide, with a combination of atomic layer deposited and plasma enhanced chemical vapor deposited SiO2 layers, is used to enhance the breakdown voltage of spin-on-glass source/drain doped lateral Ga2O3 MOSFET. Three terminal breakdown voltage measured in Fluorinert ambient reaches 1850 V for a ${L}_{\textsf {gd}}= \textsf {20}\,\,\mu \text{m}$ device. This is the first report of lateral Ga2O3 MOSFET with more than 1.8 kV breakdown voltage. For a device with ${L}_{\textsf {gd}}= \textsf {1.8}\,\,\mu \text{m}$ , the average electric field strength is calculated to be 2.2 ± 0.2 MV/cm while the field simulation of the device shows a peak field of 3.4 MV/cm.

Abstract: Recent demonstration of aggressively scaled HfO2-based ferroelectric field effect transistors (FE-HfO2-FETs) has illustrated a pathway to fabricate FeFETs that enjoy COMS-compatibility, low power, fast switching speed, scalability, and long retention. One potential issue of this promising technology is its limited endurance, which has been attributed to the degradation of gate stack before the fatigue of polarization in the ferroelectric HfO2 layer. Some associated work has identified charge trapping and trap generation as key villains, but a clear understanding of two aforementioned underlining mechanisms is still missing. In this letter, we initiated this letter to investigate the roles of charge trapping and trap generation in causing endurance failure of FE-HfO2 FETs.

Abstract: In this letter, we report on demonstrating high-performance field-plated lateral $\beta $ -Ga2O3 Schottky barrier diode (SBD) on a sapphire substrate with a reverse blocking voltage of more than 3 kV and a low dc specific ON-resistance ( ${R}_{{ \mathrm{\scriptscriptstyle ON}, \text {sp}}}$ ) of 24.3 $\text{m}\Omega \cdot $ cm2 at an anode–cathode spacing ( ${L}_{\text {AC}}$ ) of $24~\mu \text{m}$ . To the best of our knowledge, this lateral breakdown voltage (BV) >3 kV with dc power figure-of-merit (FOM) >370 MW/cm2 is the highest BV achieved among all the $\beta $ -Ga2O3 SBDs. Meanwhile, lateral $\beta $ -Ga2O3 SBD with ${L}_{\text {AC}} = \text {16}\,\,\mu \text{m}$ also demonstrates a high BV of 2.25 kV and low ${R}_{{ \mathrm{\scriptscriptstyle ON}, \text {sp}}} = \text {10.2}\,\,\text{m}\Omega \cdot $ cm2, yielding a record high dc power FOM of 500 MW/cm2. Combining with 109 high-current ON/OFF ratio, 1.15-eV Schottky barrier height and 1.25 ideality factor, $\beta $ -Ga2O3 SBD with field-plate structure shows its great promise for power electronics applications.

Abstract: In this letter, effects of top electrodes (TEs) on ferroelectric properties of Hf0.5 Zr0.5 O2 (HZO) thin films are examined systematically. The remnant polarization (Pr) of HZO thin films increases by altering TEs with lower thermal expansions coefficient ( $\alpha $ ). The largest 2Pr value of 38.72 $\mu \text{C}$ /cm2 is observed for W TE with $\alpha = 4.5\times 10^{\mathsf {-6}}$ /K, while the 2Pr value is only $22.83~\mu \text{C}$ /cm2 for Au TE with $\alpha = 14.2\times 10^{\mathsf {-6}}$ /K. Meanwhile, coercive field (Ec) shifts along the electric field axis and the offset is found to be dependent on the difference of workfunctions (WFs) between TE and TiN bottom electrode (BE). Ec shifts toward negative/positive direction, when the WF of TE is larger/smaller (Pt, Pd, Au/W, Al, Ta) than TiN BE. This letter provides an effective way to modulate HfO2-based device performance for different requirements in actual application.

Abstract: A highly scalable synapse device based on a junctionless (JL) ferroelectric (FE) FinFET is presented for neuromorphic applications. The synaptic behaviors of the JL metal-ferroelectric-insulator-silicon FinFET were experimentally demonstrated after verifying the ferroelectric characteristics of the HfZrO X (HZO) film using a metal-ferroelectric-metal capacitor. The fabricated synapse showed distinguishable polarization switching behaviors with gradually controllable channel conductance. From neural network simulations using the proposed JL FE FinFET as synapses, the pattern recognition accuracy for hand-written digits was validated to be approximately 80% for neuromorphic applications.

Abstract: The impacts of static and dynamic gate stress on the threshold voltage ( ${V}_{\text {TH}}$ ) instability in Schottky-type ${p}$ -GaN gate AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. ${V}_{\text {TH}}$ shifts negatively under large positive bias static stress ( ${V}_{\text {G}}\_ {\text {stress}} > 5$ V) by adopting conventional quasi-static characterization techniques. In contrast, ${V}_{\text {TH}}$ under fast-dynamic-stress exhibits positive shift, and a positive frequency dependence occurs within a wide range of frequency from 10 Hz to 1 MHz. The different ${V}_{\text {TH}}$ instability behavior under static and dynamic stress mainly originates from the time-dependent charges (electrons and holes) storage/release mechanisms in the ${p}$ -GaN layer, which is floating in the Schottky-type ${p}$ -GaN gate HEMT.

Abstract: Resistance random access memories (RRAM) or memristors with an analog change of conductance are widely explored as an artificial synapse, e.g., Pr0.7Ca0.3MnO3 (PCMO) RRAM-based synapses. In addition to synapses, scaled neurons are essential to enable a neuromorphic hardware. In this letter, we propose a PCMO RRAM for integrate and fire (IF) neuron. The analog conductance increase during SET process enables integration function. Upon exceeding a conductance threshold (i.e., fire) during a READ operation, a hard RESET is performed to reduce the conductance. The SET, READ, and RESET are performed in different phases of a clock to enable a PCMO for IF neuron. The availability of a non-volatile PCMO-based synapse makes PCMO for IF neuron attractive. Finally, PCMO-based neuron in spiking neural network yields software-equivalent classification accuracy as demonstrated on standard Fischer’s Iris flower data set.

Abstract: In this letter, we investigate the threshold voltage ( ${V}_{\text {TH}}$ ) shift in a p-GaN gate AlGaN/GaN transistor by designed gate-bias pulse measurements. It was found that the forward gate bias causes positive ${V}_{\text {TH}}$ shift. The dynamics of electron trapping was revealed from the dependences of the consequent ${V}_{\text {TH}}$ shift on the bias duration at different voltages. A time constant smaller than 0.1 ms for the ${V}_{\text {TH}}$ shift saturation at 6-V gate bias was obtained. It was also found that the ${V}_{\text {TH}}$ became inversely proportional to the gate-bias voltages exceeding 7 V. This inverse proportionality of the ${V}_{\text {TH}}$ shift resulted from the threshold of the hole-injection/electroluminescence (EL) and the sequential optical pumping effect on the electron traps. The EL emission was confirmed by a self- and in-situ photon detection measurement.

Abstract: The adsorption of gas molecules, such as N2, O2, CO2, H2O, CO, NO, NO2, H2S, NH3, and SO2 on monolayer C3N has been investigated by means of first-principles and non-equilibrium Green’s function calculations. We show that monolayer C3N is preferable for the NO2 and SO2 molecules with suitable adsorption strength and apparent charge transfers. Moreover, the ${I}$ – ${V}$ characteristics of C3N show clear variations after the adsorption of NO2 and SO2. Such sensitivity and selectivity to NO2 and SO2 molecules make C3N a promising candidate for highly sensitive gas sensor.

Abstract: We report silicon delta-doped $\beta $ -Ga2O3 metal semiconductor field effect transistors (MESFETs) with source–drain ohmic contacts formed by patterned regrowth of n-type Ga2O3. We show that regrown n-type contacts can enable a lateral low-resistance contact to the two-dimensional electron gas channel, with contact resistance lower than $1.5~\Omega $ -mm. The fabricated MESFET has a peak drain current ( ${I} _{D,\text{MAX}}$ ) of 140 mA/mm, transconductance ( ${g} _{m}$ ) of 34 mS/mm, and 3-terminal off-state breakdown voltage of 170 V. The proposed device structure could provide a promising path towards vertically scaled $\beta $ -Ga2O3 field effect transistors.

Abstract: We report a high-performance vertical GaN-on-GaN Schottky barrier diode (SBD) with a planar nitridation-based termination (NT) technique. The developed NT-SBD with nearly ideal Schottky contact exhibits a forward current density over kA/cm2, current swing over 1013, and differential specific ON-resistance of 1.2 $\text{m}\Omega \cdot $ cm2. The breakdown voltage is boosted from 335 V for unterminated-SBD to 995 V after termination, whereas a high ON/OFF current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ at −600 V) of ~108 is realized in the NT-SBD. It has been verified that the NT technique can favorably modify GaN surface condition, leading to suppressed leakage current at the junction edge and enhanced breakdown voltage.

Abstract: We report the investigation of negative differential resistance (NDR) in negative capacitance (NC) germanium (Ge) pFETs. The NDR in NC transistors is attributed to the coupling of drain voltage to the internal gate voltage ${V}_{\text {int}}$ via the gate-to-drain capacitance. It is demonstrated that NDR strongly depends on the matching between the NC induced by ferroelectric capacitance ${C}_{\text {FE}}$ and the positive capacitance associated with the underlying transistor capacitance ${C}_{\text {MOS}}$ . For the non-hysteretic devices, NDR gets pronounced with an increased thickness of ferroelectric film ${t}_{\text {fe}}$ and ${V}_{\text {GS}}$ . This is attributed to the fact that the drain coupling factor is improved with an increased ${t}_{\text {fe}}$ and ${V}_{\text {GS}}$ , leading to the better matching between ${C}_{\text {FE}}$ and ${C}_{\text {MOS}}$ . For the hysteretic NC transistors, however, NDR is only obtained at the lower ${V}_{\text {GS}}$ , but not observed at higher ${V}_{\text {GS}}$ .

Abstract: A 3.2-in flexible color display, with a resolution of 50 ppi and composed of bottom-emission multiphoton organic light-emitting diodes (OLEDs) and inkjet-printed organic thin-film transistors (OTFTs) with a bottom-gate/bottom-contact structure on a color filter, was developed. The device could successfully display color videos while being bent, and achieved a maximum luminance of 125 cd/m2 with white light emission. The gate dielectrics of the OTFTs used on the backplane were bilayers of cardo polymer and Parylene, and the material used for the organic semiconductors was dithieno [2,3-d;2’,3’-d’]benzo[1,2-b;4,5-b’]dithiophene blended with polystyrene in tetralin solvent, which was coated using inkjet printing to sufficiently fill the banks composed of a fluorine-based polymer. OTFTs with a channel length of 5 $\mu \text{m}$ were created using the above process, and the structure achieved a high mobility of 1.2 $\mathrm {cm}^{{{2}}}/({\mathrm{ V}}\cdot \text{s}$ ), making it suitable for flexible color OLED displays. The mobility was about three times as high as that obtained using solution shearing methods.

Abstract: In this letter, the write disturb of Hf0.5Zr0.5O2-based 1T-FeFET nonvolatile AND memory array is experimentally investigated for ${V}_{W}$ /2 and ${V}_{W}$ /3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low- ${V}_{\textsf {TH}}$ erased state and the increased read current of the high- ${V}_{\textsf {TH}}$ programmed state are the key factors that limit the maximum array size.

Abstract: Inspired by the neocortex of the human brain, neuromorphic systems are favorable for processing a variety of complex tasks, such as recognition, prediction, and optimization. To build such an intelligent system, neuromorphic devices are in high demand. Here, photoelectric neuromorphic devices based on pulse light-stimulated low-voltage indium–gallium–zinc-oxide electric-double-layer transistors were investigated. Such devices can mimic some important synaptic behaviors, such as excitatory post-synaptic potentials, paired-pulse facilitation, and long-term plasticity in the form of photonic excitatory post-synaptic potentials. At last, depression mode to potentiation mode transition was also demonstrated by gate voltage modulation. Our photoelectric neuromorphic devices are interesting for photonic neuromorphic systems.

Abstract: Flexible pressure sensors are crucial for E-skins to enable tactile sensing capabilities. However, flexible pressure sensors often exhibit high hysteretic response caused by internal and external mechanical dissipations in flexible materials. The hysteresis gives rise to reliability issues, especially in the presence of dynamic stress. In this letter, we report a flexible capacitive pressure sensor design with hierarchically microstructured electrodes to obtain both high sensitivity and low hysteresis. The sparsely spaced large pyramid microstructure improves the sensitivity, whereas the small pyramid reduces the hysteresis caused by interfacial adhesion. The optimized sensor shows excellent performances in terms of high sensitivity (~3.73 kPa−1), ultralow detection limits (0.1 Pa), significantly reduced hysteresis (~4.42%), and enhanced sensing capability for pluses, which demonstrates its potential for advanced electronic skins.

Abstract: Slow-wave structure (SWS) is a core part of a traveling-wave-tube (TWT) amplifier. In this letter, the planar microstrip meander SWS on a dielectric substrate at $V$ -band (50–70 GHz) is studied. The basic electromagnetic parameters of the SWS are calculated. The SWS circuits are designed and fabricated, and good transmission characteristics are measured. The SWS developed is characterized by a wide bandwidth and a relatively-large slow-wave factor, and is suitable for a low-voltage TWT with the sheet electron beam.

Abstract: A high frequency hydrogen-terminated diamond metal-insulator-semiconductor field-effect transistor (MISFET) with extremely small source-drain distance of about 350 nm was realized by self-aligned process on (001)-oriented single crystal diamond substrate. To suppress the gate leakage current, a low temperature Al2O3 film was deposited as the gate insulator by inductance coupled plasma enhanced atomic layer deposition. A low ohmic contact resistance of $1.84~\Omega \cdot $ mm was measured by using transmission line method. The fabricated 100 nm gate length MISFET shows a high current density of 585 mA/mm and a high transconductance of 206 mS/mm. By minimizing the parasitic parameters of the device, a high current gain cut-off frequency ${f} _{\textsf {T}}$ of 70 GHz and maximum frequency of oscillation ${f} _{\textsf {max}}$ of 80 GHz have been realized.

Abstract: We present broadband high sensitivity terahertz (THz) detectors based on 90 nm CMOS technology with the state-of-the-art performance. The devices are based on bow-tie and log-spiral antenna-coupled field-effect transistors (FETs) for the detection of free-space THz radiation (TeraFETs). We report on optimized performance, which was achieved by employing an in-house developed physics-based model during detector design and thorough device characterization under THz illumination. The implemented detector with bow-tie antenna design exhibits a nearly flat frequency response characteristic up to 2.2 THz with an optical responsivity of 45 mA/W (or 220 V/W). We have determined a minimum optical noise-equivalent power as low as 48 pW/ $\sqrt {\textsf {Hz}}$ at 0.6 THz and 70 pW/ $\sqrt {\textsf {Hz}}$ at 1.5 THz. The results obtained at 1.5 THz are better than the best narrowband TeraFETs reported in the literature at this frequency and only up to a factor of four inferior to the best narrowband devices at 0.6 THz.

Abstract: We demonstrate the first GaN vertical transistor on silicon, based on a 6.7- $\mu \text{m}$ -thick n-p-n heterostructure grown on 6-inch silicon substrate by metal organic chemical-vapor deposition. The devices consist of trench-gate quasi-vertical metal–oxide–semiconductor field-effect transistors with a 4- $\mu \text{m}$ -thick drift layer, exhibiting enhancement-mode operation with a threshold voltage of 6.3V and an ON/OFF ratio of over 108. A high OFF-state breakdown voltage of 645 V along with a specific ON-resistance of $6.8~\textsf {m}\Omega \cdot \textsf {cm}^{{\textsf {2}}}$ were achieved thanks to the high-quality 4- $\mu \text{m}$ -thick GaN drift layer, presenting a relatively low defect density and very high electron mobility (720 cm $^{{\textsf {2}}}/\textsf {V}\cdot \textsf {s}$ ). This excellent performance represents a major step toward the realization of high-performance GaN vertical power transistors on low-cost silicon substrates.

Abstract: Ferroelectric Zr-doped HfO2 (HZO) is a promising candidate for steep slope transistors and memory technology. For these applications, it is essential to understand and optimize the switching dynamics of the ferroelectric film. In this letter, we characterize the polarization reversal of an 8 nm-thick HZO film deposited by the atomic layer deposition with voltage pulses varying in amplitude (0.8–2 V) and duration (200 ns–7.6 ms). We show that the measurements are well described by a nucleation limited switching model, which enables extraction of the minimum switching time and the probability distribution of local electric field variations in the polycrystalline film. The close model fit spanning 5 orders of magnitude in pulse duration indicates the applicability of this model to HZO. This characterization framework can be used to quantify, compare, and optimize the switching dynamics of ferroelectric HZO.

Abstract: A high-performance solar-blind photodetector based on Cr-doped gallium oxide (Ga2O3) has been fabricated. A 140-nm-thick Ga2O3 layer was mechanically exfoliated from bulk crystal. The photodetector was based on a field-effect transistor structure, which showed a very high photo-to-dark current ratio larger than 106 and excellent current saturation. When the photodetector was tested with a 254-nm ultra-violet light, the ratio of drain current with and without the UV light reached nearly six orders of magnitude. The dark current was as low as 5 pA. Furthermore, the current rise time and decay time were both about 25 ms. High responsivity of ${4.79} \times {10}^{{5}}$ A/W and external quantum efficiency of ${2.34} \times {10}^{{6}}$ also have been achieved at the same time.

Abstract: Threshold voltage instability was observed on $\beta $ -Ga2O3 transistors using double-pulsed current–voltage and constant drain current deep level transient spectroscopy (DLTS) measurements. A total instability of 0.78 V was attributed to two distinct trap levels, at ${E}_{C}$ -0.70 and ${E}_{C}$ -0.77 eV, which need to be mitigated for future applications. The traps are likely located near the gate–drain edge and below the delta-doped layer, which is determined through the DLTS technique and an understanding of the fill and empty biasing conditions. The trap modulation was consistent with a gate leakage-based trap filling mechanism, which was demonstrated. It is likely that Fe is playing a role in the observed dispersion due to the close proximity of the Fe substrate.

Abstract: Nitrogen polar (N-Polar) GaN high-electron-mobility transistors (HEMT) targeting high-voltage switching applications were fabricated on epi-layers grown by metal-organic chemical vapor deposition on sapphire substrates. Devices demonstrated a combination of high breakdown voltage and low dynamic ON-resistance. Breakdown voltages of over 2000 V were observed on transistors with ${L}_{G}=\text {1}\,\,\mu \text{m}$ , ${L}_{{\text {GS}}}=1\,\,\mu \text{m}$ , and ${L}_{{\text {GD}}}=28\,\,\mu \text{m}$ . These devices had a drain current density of ~ 575 mA/mm at ${V}_{{\text {GS}}}=1$ V, and the specific ON-resistance (active-area) was $ {4}~\text {m}\Omega \cdot \text {cm}^{2}~(10~\Omega \cdot \text {mm}$ ). Dynamic ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) was characterized $\text {5}~\mu \text{s}$ after the device was turned ON, with up to 575-V OFF-state stress. At ${V}_{{\text {DS}}, {Q}} = \text {575}$ V, the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ was ~1.4 times the static ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (40% increase). These transistors showed an ultra-low dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of ~5% when measured at 450-V stress. As one of the first demonstrations of N-Polar GaN HEMTs for power switching applications, the devices discussed in this letter achieve excellent ${V}_{ \mathrm{\scriptscriptstyle BR}}$ and dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ performance comparable to (and in most cases better than) the state-of-the-art Ga-Polar GaN HEMTs reported in the literature.

Abstract: We demonstrate the hardware implementation of spiking neural network (SNN) with synaptic transistors and neuron circuits. The method of conversion from software fully-connected network (FCN) to hardware SNN with little degradation is discussed. The degradation of classification accuracy is analyzed in terms of device variation and noisy images. In addition, the accuracy degradation is significantly improved by stacking denoising autoencoder (DAE) layer. FCN–SNN conversion with very little performance drop is demonstrated using weight normalization, and SNN with DAE layer shows a great tolerance to input image noise.

Abstract: Hafnium oxide-based ferroelectric field-effect transistors (FeFETs) have a great potential for fast nonvolatile memory due to their high performance, fully CMOS compatible integration, and low-power operation. The aggressive scaling of these devices has revealed novel features, such as the multilevel storage capability and abrupt switching, which, however, appears to be a stochastic process. In this letter, we propose a path for true random number generation based on the statistical switching in a single FeFET device. It relies on an inherent randomness of the polarization reversal of ferroelectric domains in the gate stack. The bit sequence is generated by repeatedly programming an FeFET at a calibrated voltage and pulse width, and features random and equiprobable “ones” and “zeros,” which are separated by orders of magnitude in drain current. This simple yet reliable operation provides a compact one-transistor solution for the unbiased random number generation.

Abstract: This letter demonstrates a novel technology to fabricate fully vertical GaN-on-Si power diodes with state-of-the-art performance. Si substrate and buffer layers were selectively removed and the bottom cathode was formed in the backside trenches extending to an n+-GaN layer. A specific differential ON-resistance of 0.35–0.4 $\text{m}\Omega \cdot $ cm2 (normalized to the total device area) and a breakdown voltage of 720 V were demonstrated in this novel fully vertical GaN-on-Si p-n diode, rendering a Baliga’s figure of merit over 1.5 GW/cm2. These results set a new record performance in all vertical GaN power diodes on foreign substrates, and demonstrate the feasibility of making fully vertical GaN-on-Si power diodes and transistors by selective removal of Si substrates and buffer layers.