Abstract: In this letter, we report for the first time a distinctive approach of implementing a junctionless transistor (JLT) without doping (doping-less) the ultrathin silicon film. A charge-plasma concept is employed to induce n-region for the formation of source and drain for a n-channel JLT using appropriate metal work function electrodes. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped JLT of identical dimensions. In conventional JLTs, the channel doping concentration is generally kept high to ensure high ON-state current, but it causes variation in threshold voltage, which may be due to process variations. The proposed device solves the problem of threshold voltage variability without affecting inherent advantages of JLTs.

Abstract: This letter demonstrates GaN vertical Schottky and p-n diodes on Si substrates for the first time. With a total GaN drift layer of only 1.5- $\mu{\rm m}$ thick, a breakdown voltage (BV) of 205 V was achieved for GaN-on-Si Schottky diodes, and a soft BV higher than 300 V was achieved for GaN-on-Si p-n diodes with a peak electric field of 2.9 MV/cm in GaN. A trap-assisted space-charge-limited conduction mechanism determined the reverse leakage and breakdown mechanism for GaN-on-Si vertical p-n diodes. The on-resistance was 6 and 10 ${\rm m}\Omega\cdot{\rm cm}^{2}$ for the vertical Schottky and p-n diode, respectively. These results show the promising performance of GaN-on-Si vertical devices for future power applications.

Abstract: The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N + pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N + pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N + pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N + pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N + pocket p-n-p-n TFET exhibits a higher I ON (~20 times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N + pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend.

Abstract: A diamond metal-semiconductor field-effect transistor (MESFET) with a Pt Schottky gate was fabricated. The MESFET exhibited clear saturation and pinchoff characteristics. The drain current of the MESFET operated at 300 °C was 20 times higher than that at room temperature due to the activation of acceptors. The breakdown voltage was highly dependent on the gate-drain length and reached 1.5 kV at a gate-drain length of 30 μm, which is the highest reported for a diamond FET.

Abstract: Under realistic switching conditions, SiC MOSFETs reliability issues remain as a challenge that requires further investigation. In this letter, a specific aging test has been developed to monitor and characterize the electrical parameters of the SiC MOSFET. This allows estimations of the health state and predictions of the remaining lifetime prior to its failure. The gate leakage current seems to be a relevant runaway parameter just before failure. This leakage indicates deterioration of the gate structure. This hypothesis has been validated through analysis of scanning electron microscopy pictures, with a focused ion beam cut showing cracks within the polysilicon.

Abstract: The power consumption of capacitor leakage current, increase of the capacitor aspect ratio, and lack of higher dielectric constant (κ) material are the difficult challenges to downscaling dynamic random access memory (DRAM). This letter reports a new one-transistor ferroelectric-MOSFET (1T FeMOS) device that displays DRAM functions of a 5 ns switching time, 1012 on/off endurance cycles, and 30 times on/off retention windows at 5 s and 85 °C. A simple 1T process and a considerably low OFF-state leakage of 3×10-12 A/μm were achieved. This novel device was achieved by applying ferroelectric ZrHfO gate dielectric to a p-MOSFET, which is fully compatible with existing high-κ CMOS processing.

Abstract: The device performance of silicon nanotube field effect transistor (Si-NT-FET) having tubular channel and controllable by an inner and outer gates is presented. The inner and outer gates render effective charge control inside the channel providing the Si-NT-FETs excellent immunity to short channel effects. Evaluations of electrical performances of Si-NT-FET using well calibrated 3D device simulations show that Si-NT-FETs can outperform Si-nanowire (NW)-FETs in terms of drive currents and SCEs. Our evaluation further shows that Si-NT-FETs can provide ~2× higher drive current compared to Si-NT-FET of the same diameter. This excellent electrical performance makes Si-NT-FETs promising candidates to extend CMOS scaling roadmap beyond Si-NW-FET.

Abstract: A feasibility and performance study of electrically reconfigurable nanowire transistors with selectable pFET and nFET operations is presented. The challenges toward circuit implementation are evaluated based on transient simulations of logic circuits. A novel physical structure capable of computing a NAND as well as NOR function is introduced. The new approach provides a flexible platform to develop and test fine-grain reconfigurable circuits and systems.

Abstract: We propose another process for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO 2 /4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 cm 2 /Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO 2 may be responsible for the reduced trap density and enhanced channel mobility.

Abstract: To fabricate gate recessed normally-off AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors, we have employed a novel SiNx/HfO2 dual gate insulator. A plasma enhanced atomic layer deposition (PEALD) technique was used for very thin high quality SiNx (5 nm) as an interfacial layer followed by RF-sputtered HfO2 as a high- k dielectric for the second gate insulator structure. The PEALD SiNx interfacial layer effectively suppresses the forward gate leakage current and the current collapse. We have achieved excellent characteristics such as large threshold voltage of 1.65 V, high breakdown voltage of 900 V, extremely small off-state drain leakage current less than 10-9 A/mm and high ON/OFF drain current ratio of ~ 109, low on-state resistance of 1.84 mΩ·cm2, and small subthreshold slope of 85 mV/decade.

Abstract: This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate The exposure to OFF-state bias induces a significant increase in the ON-resistance (R on ) of the devices Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) R on -increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the R on -increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length

Abstract: We report a high-performance normally-off Al 2 O 3 /AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al 2 O 3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm 2 /V·s, a high on/off drain current ratio of ~10 10 , and low dynamic on-resistance degradation.

Abstract: This letter reports high performance AlGaN solar-blind avalanche photodiodes (APDs) with separate absorption and multiplication structure grown by metal-organic chemical vapor deposition on AlN templates. In fabricating APD devices, we applied a photo-electrochemical treatment process after mesa etching to reduce damage induced by etching. After introducing this process, the leakage current of the fabricated devices was reduced obviously and a record-high gain of 1.2×104 at the reverse bias of 84 V was achieved under the measurement condition with the protection current constrained to 10-5 A.

Abstract: In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an \(L_{\mathrm {\mathbf {G}}}\) of 60 nm an extrinsic \(g_{\mathrm {\mathbf {m}}}\) of \(1030~\mu \) S \(/\mu \) m at \(V_{\mathrm {\mathbf {ds}}} = 0.5\) V is achieved which is a \(1.75\times \) increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to \(D_{\mathrm {{it}}}\) resulting in an SS \(_{\mathrm {{SAT}}}\) of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm \(L_{\mathrm {{G}}}\) devices.

Abstract: We demonstrate an efficient approach to engineer the dielectric/AlGaN positive interface fixed charges by oxygen plasma and post-metallization anneal. Significant suppression of interface fixed charges from 2 × 1013 to 8 × 1012 cm-2 was observed. Experimental and theoretical electron mobility characteristics and the impact of remote impurity scattering were investigated. The reduction in oxide/semiconductor interface charge density leads to an increase of electron mobility, and enables a positive threshold voltage.

Abstract: Monolithic integration of high-performance AlGaN/GaN high-electron mobility transistors (HEMTs) and blue light emitting diodes (LEDs) on sapphire substrates has been demonstrated by metal organic chemical vapor deposition selective growth technique. The integrated HEMT-LED exhibits a peak transconductance (Gm) of 244 mS/mm, a maximum drain current (Id) of 920 mA/mm, and an ON-resistance (Ron) of 2.6 Ω·mm. The forward voltage (VF) of the LED is 3.1 V under an injection current of 10 mA. The integrated LED emits modulated light power efficiently at a wavelength of 470 nm by a serially connected GaN HEMT, showing potential applications such as solid-state lighting, displays, and visible light communications.

Abstract: A novel nonvolatile flip-flop based on spin-orbit torque magnetic tunnel junctions (SOT-MTJs) is proposed for fast and ultralow energy applications A case study of this nonvolatile flip-flop is considered In addition to the independence between writing and reading paths, which offers a high reliability, the low resistive writing path performs high-speed, and energy-efficient WRITE operation We compare the SOT-MTJ performances metrics with the spin transfer torque (STT)-MTJ Based on accurate compact models, simulation results show an improvement, which attains 20× in terms of WRITE energy per bit cell At the same writing current and supply voltage, the SOT-MTJ achieves a writing frequency 4× higher than the STT-MTJ

Abstract: Light-emitting diode (LED) is one of the most important light sources due to its low power consumption and long lifetime In this letter, we present the high-frequency characteristics of GaN-based green LEDs with different aperture diameters In order to get higher current density, we use ring-shaped electrode to confine the current injection Unlike conventional LEDs, we only use its natural feature to get a high modulation bandwidth The LEDs investigated have a peak emission wavelength of 500 nm The highest optical 3-dB modulation bandwidth is ~463 MHz at 50 mA for the 500-nm green GaN-based LED with an aperture diameter of 75 μm It is the highest bandwidth yet reported for the green GaN-based LEDs The LED also exhibits a relatively high output power of ~16 mW at 50 mA as compared with other high-speed LEDs Such the LEDs can be applied to plastic optical fiber and visible light communication in the future

Abstract: This letter evaluates temporal and thermal stability of a state-of-the-art few-layer phosphorene MOSFET with Al2O3 surface passivation and Ti/Au top gate. As fabricated, the phosphorene MOSFET was stable in atmosphere for at least 100 h. With annealing at 200 °C in dry nitrogen for 1 h, its drain current increased by an order of magnitude to $\sim 100$ mA/mm, which could be attributed to the reduction of trapped charge in Al2O 3 and/or Schottky barrier at the source and drain contacts. Thereafter, the drain current was stable between −50 °C and 150 °C up to at least 2000 h. These promising results suggest that environmental protection of phosphorene should not be a major concern, and passivation of phosphorene should focus on its effect on electronic control and transport as in conventional silicon MOSFETs. With cutoff frequencies approaching the gigahertz range, the present phosphorene MOSFET, although far from being optimized, can meet the speed and stability requirements of most flexible electronics for which phosphorene is intrinsically advantageous due to its corrugated lattice structure.

Abstract: Ballistic device performance of monolayer black phosphorous (BP) field-effect transistors (FETs) is investigated in this letter. Due to the anisotropic effect mass of the carriers, the ON-state current is dependent on the transport direction. The effective masses are lower in the armchair direction, which provides higher drive current at the same biasing. The degree of anisotropy is higher for the holes, which improves the performance of p-type devices. The intrinsic delay of 20-nm BP FETs is in the range of 50 fs at ON-/OFF-current ratio of four orders. Monolayer BP FETs outperform both MoS 2 and Si FETs for both nand p-type devices in terms of ballistic performance limits, due to highly anisotropic band structure.

Abstract: AlGaN/GaN high electron mobility transistors grown on Si, SiC, and sapphire substrates were exposed to 2-MeV proton irradiation in incremental fluences up to 6 × 10 14 cm -2 . The devices were characterized initially and after each irradiation by Hall and dc I-V measurements to probe the mechanisms associated with radiation-induced degradation and failure. It was determined that defects created at the AlGaN/GaN interface introduce scattering centers near the two-dimensional electron gas (2DEG), which result in degraded mobility. Additionally, charged traps in the structure serve to screen the 2DEG resulting in reduced sheet carrier density. These two effects are responsible for degraded I-V behavior, including reduced saturation current and transconductance, increased ON-resistance, and positive threshold voltage shift. Interestingly, the sample with the most pre-existing defects was the most tolerant of radiation-induced damage.

Abstract: A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature ...

Abstract: A GaN MIS-HEMT with nitrogen (N)-passivation for power device applications is demonstrated. In this letter, nitrogen radicals were adopted to recover nitrogen-vacancy-related defects which were formed due to the thermal decomposition and evaporation of nitrogen atoms from GaN surface during high-temperature process. Besides, nitrogen radicals can also remove impurities and reduce surface dangling bonds by forming Ga-N bonds on the SiN/GaN interface. With N-passivation, the device shows high ON/OFF current ratio, steep subthreshold slope, low OFF-state leakage current, high breakdown voltage, and improved dynamic ON-resistance. The device reliability under high-electric field stress was also improved as a result.

Abstract: This letter studies the correlation of postannealing treatment on the electrical performance of amorphous In-Zn-Sn-O thin-film transistor (a-IZTO TFT). The 400 °C annealed a-IZTO TFT exhibits a superior performance with field-effect mobility of 39.6 cm \(^{{\mathbf {2}}}\) /Vs, threshold voltage ( V \(_{\rm th}\) ) of −2.8 V, and subthreshold swing of 0.25 V/decade. Owing to the structural relaxation by 400 °C annealing, both trap states of a-IZTO film and the interface trap states at the a-IZTO/SiO2 interface decrease to \(2.16\!\times \! 10^{{\mathbf {17}}}\) cm \(^{\mathbf {-3}}\) eV \(^{{\mathbf {-1}}}\) and \(4.38\times 10^{\mathbf {12}}\) cm \(^{\mathbf {-2}}\) eV \(^{\mathbf {-1}}\) , respectively. The positive bias stability of 400 °C annealed a-IZTO TFTs is also effectively improved with a V \(_{\rm th}\) shift of 0.92 V.

Abstract: In this letter, flexible double-gate (DG) thin-film transistors (TFTs) based on InGaZnO4 and fabricated on free standing plastic foil, using self-alignment (SA) are presented. The usage of transparent indium-tin-oxide instead of opaque metals enables SA of source-, drain-, and top-gate contacts. Hence, all layers, which can cause parasitic capacitances, are structured by SA. Compared with bottom-gate reference TFTs fabricated on the same substrate, DG TFTs exhibit a by 68% increased transconductance and a subthreshold swing as low as 109 mV/dec decade (-37%). The clockwise hysteresis of the DG TFTs is as small as 5 mV. Because of SA, the source/drain to gate overlaps are as small as ≈ 1 μm leading to parasitic overlap capacitances of 5.5 fF μm-1. Therefore a transit frequency of 5.6 MHz is measured on 7.5 μm long transistors. In addition, the flexible devices stay fully operational when bent to a tensile radius of 6 mm.

Abstract: In this letter, we investigated the behaviors of surface- and buffer-induced current collapse in AlGaN/GaN high-electron mobility transistors (HEMTs) using a soft-switched pulsed \(I-V\) measurement with different quiescent bias points. It is found that the surface- and buffer-related current collapse have different relationship with the gate and drain biases ( V \(_{\mathrm { {\!GS0,}}}\) V \(_{\mathrm { {\!DS0}}}\) ) during quiescent bias stress. The surface-induced current collapse in devices without passivation monotonically increases with the negative V \(_{\mathrm { {\!GS0}}}\) , suggesting that an electron injection to the surface from gate leakage is the dominant mechanism and the Si3N4 passivation could effectively eliminate such current collapse. The buffer-induced current collapse in devices with intentionally carbon-doped buffer layer exhibits a different relationship with V \(_{\mathrm { {\!GS0}}}\) after surface passivation. The buffer-related current collapse shows a bell-shaped behavior with V \(_{\mathrm { {\!GS0}}}\) , suggesting that a hot electron trapping in the buffer is the dominant mechanism. The soft-switched pulsed \(I-V\) measurement provides an effective method to distinguish between the surface- and buffer-related current collapse in group III-nitride HEMTs.

Abstract: In this letter, we examine the role of the Ti capping layer in HfO x -based resistive random access memory (RRAM) devices on the memory performance. It is found that with a thicker Ti capping layer, the fresh device initial leakage current increases and as a result, the forming voltage decreases. In addition, with a thin Ti layer of <;3 nm (on top of 8-nm HfO x ), there is no resistive switching, while by inserting a thicker Ti layer of 10 nm, the memory window enlarges to about two orders. Very good uniformity has also been observed in thick Ti capping devices, demonstrating the effectiveness in RRAM device engineering. It is believed that the Ti layer serves as an oxygen reservoir, by extracting oxygen during device formation and electrical forming process and facilitates resistive switching thereafter.

Abstract: In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with p-doped compressively strained Si 0.5 Ge 0.5 source, intrinsic Si channel, and n-doped Si drain. We observe a linear relation of gate length, L g , and ON-current, I ON , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.

Abstract: This letter introduces a novel inductively coupled plasma-reactive ion etching (ICP-RIE) technique based on a BCl3/SiCl4/Ar chemistry for fabricating sub-20 nm diameter InGaAs nanowires with smooth, vertical sidewall and high aspect ratio (>10). To mitigate dry-etch damage, RIE is followed by a digital etch method comprised of multiple cycles of self-limiting low power O2 plasma oxidation and diluted H2SO4 rinse. Using these technologies, we demonstrate vertical InGaAs gateall-around nanowire MOSFETs with 30 nm diameter. Digital etch improves both the subthreshold swing and peak transconductance, indicating enhanced sidewall interfacial quality. The combination of RIE and digital etch techniques proposed here is promising for future 3-D III-V MOSFETs.