Abstract: Negative-bias temperature instability(NBTI)is a major challenge for modern integrated circuits manufacture In this paper,We discuss the results of such stress on device and circuit Performance NBTI is approached from a process point of view,providing a general picture of the manufacturing process steps that affect NBTI performance It is found that several process steps may be optimized to reduce the NBTI suscepti-bility of p-type MOSFETs

Abstract: Based on a simple-structure package, thermal analysis with ANSYS software for high-power LED was presented. Temperature fields of different interface materials were compared. Compared with thermal stresses fields of low-temperature nanosilver sintered paste and Sn63Pb37 interface materials. The result showed that the novel low-temperature nanosilver sintering technology had better thermomechanical properties.

Abstract: A charge-pump circuit which can be used in PLL synthesizer is designed in TSMC 0.18μm CMOS process. Conventional CMOS charge pump circuits have large current mismatch. An operational amplifier and self-biasing cascode current mirror and supply-independent reference current source are used to make charge and discharge current match. Simulation results show that the charge pump current is 0.5mA,the current mismatch is less than 1μA at output voltage range of 0.3V～1.6V,with power consumption of 6.8mW at 1.8V.

Abstract: Heat dissipation is the crux of all key technologies in high-power semiconductor lasers. Semiconduc- tor lasers are inherently efficient devices capable of generating very high peak powers, which have an electrical- to-optical conversion efficiency of 40% to 50%, i.e., 50% to 60% of electric energy converts into thermal energy. The peak heat flux generated by these devices at the interface where the diode material soldered to the chip carrier is on the order of 1KW.cm-2. The thermal load there is a limitation in the average power operation of laser diodes. The solution to heat dissipation of semiconductor laser arrays and stacks will be directly related to lifetime of lasers, resulting in rapid temperature increase in active parts of lasers, thus leading to catastrophic optical damage, and sometimes burning out of semiconductor lasers. High-power laser arrays and stacks are widely used in high-power DPSSL systems and have prospects of development. Therefore, it is necessary to develop high-power laser arrays and stacks. With the fast development of high-power laser arrays and stacks, some related key techniques are worth researching.

Abstract: A new way of design and fabrication method of IC pad for flip-chip use introduced in this article. By careful design the IC pad, more than one gold stud are bumped on those new pads, and interconnections with high reliability are obtained consequently. This method can also be used for the fabrication of KGD.

Abstract: This paper describes the potting aid and process design for Outdoor LED Display Module. It is concerned with the choose of potting materials and the potting process solution. Then, this paper describes the problem and the solution of potting process.

Abstract: Since Moisture Sensitivity Level (MSL) tests are part of the international reliability qualification standards, all the microelectronics components/products have to pass these specifications. Therefore, it is important to be able to efficiently and accurately characterize and predict the moisture related material and interface behavior in the real manufacturing, processing, testing and application conditions. The success of interfacial fracture mechanics approach to analyze moisture-induced failures in IC packaging strongly depend on accurate characterization of the critical adhesion strength, Gc. However, its measurement is complicated by the fact that adhesion depends not only on moisture concentration, C, but also temperature, T, and mode mixity, ψ. This paper described our research to develop a reliable methodology for interface toughness evaluation as function of temperature, humidity and mode mixity. Our methodology includes using the four-point bending test and shaft-loaded-blister method. Dedicated specimens consisting of various types of moulding compounds bonded onto leadframe are manufactured. Besides temperature, moisture content and mode mixity effects, also the influences of surface treatment (leadframe oxidation and contamination) and production process on the interface fracture toughness are evaluated. Multi-physics-based numerical methods are used to transfer the experimental critical loads to an interface strength parameter. These analysis covers mechanical, moisture diffusion, vapor pressure, hygro-swelling and CTE-mismatch modeling. To test and improve the methodology, various effects are evaluated, such as crack-length dependency, material properties, specimen- width, displacement-rate of the upper support/shaft, etc. The results of the proposed methodology indicate, as expected, a change in interface toughness by mode mixity, moisture content and temperature. It is found that Gc decreases with increasing moisture content and temperature. The presence of moisture at the given interface is observed as the important factor in the reduction of interfacial strength (20 %～45%). Furthermore, Gc increases by a factor 3～4 when the mode mixity shifts towards mode II.

Abstract: Epoxy molding compound(EMC), one of the largest three kinds of raw materials in semicon-ductor industry, performs the significant functions on the capabilities of discrete and IC. Gelation time and spiral flow length, the basic performance indexes, directly define the process parameters. However, the temperature affects them greatly. The temperature conditions of these procedures, such as manufacture, storage, thawing and molding etc. engender the different extent of impacts. Unapt temperature selected, may lead to the badness of molding workability, encapsulation body defect, and attenuation or fault of the semiconductors capabilities. This paper emphatically expounds the influences of temperature on the usage of EMC and the capabilities of semiconductors.

Abstract: Adopt DEMUX ( multiplexing distribute ) structure to form the tree configuration . It uses the clock sufficient, samples at the rise and down edge of the clock, so the circuit achieves higher converting speed. Based upon the CMOS technics the dissipation is decreased. By the full custom design , the performance of the circuit is optimized, the area of the layout is reduced and the security is improved. The circuit has been fabricated by CSMC 0.6μm CMOS technics .

Abstract: Conducted coupling is a kind of important in series interfere method, it is very large to the interference that leads line and electric cable. The electric capacity coupling matching and inductance coupling match are two kinds of forms that conducted coupling, passing the analysis to constitute the mechanism and principle to them, putting forward repressing a few of their methods: Match the length that can adopt to let up to lead line and enlarge the line to be apart from to the electric capacity coupling , equilibrium method the interference source and carrying on by the interference source to shield etc. the method carrys on repressing interference ; Can use to let up mutual inductance for inductance coupling, the part becomes coupling to match wreath, carrying on shield to the interference source etc.

Abstract: Recently the marketing keep requesting for electronic products,especial for consumable electronic products with smaller volume, multifunction,bigger store space and lower cost.Miniaturized and high density packages get more and more versions,for example, MCM, SiP, flip wafer, etc. Its applications are getting more and more practice. The traditional packaging hierarchy is getting not so clear because of the emergence of these new technology. No doubt, as the appearance of miniaturization and high density packages, high speed and high accuracy is more and more critical to the assembly process. The related manufacturing equipments and process shall be more advanced and flexible.Because flip wafer has more smaller outline size, smaller bump size and extra fine pitch than BGA or CSP, there are big challenges we never face in conventional surface mount process,such as bumping technology,substrate technology, the compatibilities between materials, assembly process, inspection equipments and methods.

Abstract: FPGA-based verification platform is an effective verification way of SoC, and it is becoming very important to build a prototype of the SoC before taping out. ARM Embed RISC CPU is widely used in SoC design because of high performance and low price. In this paper it discribe implementation of FPGA prototyping system for ARM7TDMI SoC Verification and the design flow, simultaneously the advantages and it discuss the disad- vantages of FPGA-based rapid prototyping of SoC verification.

Abstract: This article introduces briefly the key steps about eutectic technology in the hybrid circuit packaging. Includes the choosing of eutectic equipment and solders,fixture's design and precission manufacture,temperature prefile's setting and process experimentation.The process has a certain extent instruction in achieving multichip Eutectic.

Abstract: A kind of clock management circuit, which used in high-speed pipeline ADC, was designed. The clock management circuit with DLL as its core cell consists of bias circuit, clock input circuit, 50% duty-cycle stabiliz- ing circuit and no-overlap output circuit. The circuit is based on a 0.35μm Bi CMOS process. The measured results have shown the DLL exhibits a lock range of 70MHz~300MHz while the peak-to-peak jitter, duty-cycle and power dissipation is 16ps, 50% and 47mW at 250MHz. That is, this clock management circuit has the characteristics with high speed, good precision and low power dissipation. It’s suitable for the high-speed pipeline A/D converter.

Abstract: Currently the thermal losses of power electronic devices are increasing. At the same time, their sizes are decreasing. Consequently heat sinks have to dissipate very high heat flux densities. This paper presents the principles and characteristics of air cooling, liquid cooling, microchannel heat sink and heat pipes and intro- duces the latest research results.

Abstract: PEMs are reputed to offer significant cost,availability,size and weight advantages,but someone still focuses on reliability issues.A further objective of this paper is to make the reader aware of a number of impor- tant reliability issues which must be taken into account when PEMs are being considered for use in high reliabil- ity applications.This paper summarizes the results of a number of reliability studies which have recently been completed and presents some guidance in the procurement,test and evaluation,handling,and storage of PEMs.

Abstract: A kind of epoxy molding compounds (EMC) filled with silicon dioxide alumina and silicon nitride powder was obtained.The influence of the species and fraction of the filler on its thermal conductivity, coefficient of thermal expansion (CTE) and dielectric constant were investigated respectively.The thermal conductivity and dielectric constant of EMC improves obviously with the filler content increasing.But CTE descends sharply.At the same volume fraction,the thermal conductivity and dielectric constant of EMC filled with alumina and silicon nitride are higher than that's of the other one.But its CTE is lower than the latter.The thermal conductivity of the former reaches 2.254 W (m·K)~(-1) and the latter reaches 2.04 W (m·K)~(-1) at 60% volume fraction.And the CTE reaches 1.493×10~(-5)K~(-1)、1.643×10~(-5)K~(-1) respectively at 65% volume fraction. At the same time,the dielectric constant of this EMC can remains at a relative low lever.

Abstract: The routing switch and wire segment of interconnect resource FPGA have been analyzed concretely based on TSMC'0.35μm, three-layer metal CMOS process in this paper. The results show that employ the different logic length wire segmentation distributions and the best mixes of pass transistors and tri-state buffer switches found in this paper bring more area-delay product.

Abstract: Capsule endoscope is a micro medical instrument which embodies the whole wireless signal trans- mission system in a small volume This paper proposes micro system manufacturing with high density packag- ing technology of SiP Comparing to the traditional manufacture approach of chip customization, the SiP packaging approach has the benefits of low-cost and short development process The development of SiP technology and embedded passives in substrate technology make the micro circuit system of capsule endo- scope with commercial chips feasible

Abstract: This paper uses data from XPS analyzes the surface reaction between Al, O and F on the surface of unused, O-exposed and F-exposed Aluminum We found there will be a natural passivation layer on top of Al while when once the surface contact with F and vapor, Aluminum hydroxide fluoride will form The SEM micrographs show the surface of three samples are optically similar

Abstract: In wafer testing process,it will causes abnormal probe mark shift and probe mark out of the pad due to the changing of testing environment or prober parameters That will cause overkill and then diminish the company profit So at here,I will share my analysis and research results on abnormal probe mark shift due to temperature change during the wafer testing process

Abstract: In order to enhance the management level of street lamp system, this article presents the wireless street lamp control system based on nRF9E5 and constructs a reasonable communication agreement that implements the control of wireless jump mode of node self-correction ability. Particularly address the hardware design of system control center and the node of street lamp control, achieve the function of that design of street lamp auto control and the alarm of street lamp failure under the circumstances of dusk and dawn or lower visibility on abnormal weather in different seasons.

Abstract: The paper discusses the damage of plastic encapsulated microelectronic (PEM) devices during soaked temperature changed environment. The failure mechanism is the mismatch of coefficient of thermal expansion (CTE) between the plastic encapsulated and the chip. The failure mechanism of PEM should be exposed according to high accelerate stress test (HAST).

Abstract: In this paper,the history of FPGA is reviewed,then,the fetures of various serieses of FPGA,such as Xilinx serieses and Alrea serieses are discussedThe development directions of FPGA are givenThe impor-tant ditections are high integration,high speed,low price and system integration

Abstract: With the advancement of the modern technology and the competition situation, some factors which cannot be calculated come to be more and more important So this paper analyses the logistics network planning with AHP And focusing on the features of communication, it builds two sets of indexes to assess the location selected and the form of transition respectively