Electronics & Packaging 

Abstract: The packaging technology of three-dimension multi-chip module is an important developing direction in micro-electronic packaging technology in the future.With the developing of die package density increasing,the heat analysis and heat controlling technology for 3D MCM package becomes more and more important.In this article,thermal field of one SRAM component(stacked packaging) is analyzed using Ansys software by finite element method,and compared with the result by testing.Providing a way for reliability design or 3D MCM.

Abstract: According to the problem controling the SDRAM(Synchronous Dynamic Random Access Memory) timing in the cache the image data are complicated, presents a SDRAM controller design based on a core of FPGA(Field Programmable Gate Array). Use the thought divided module,which put the SDRAM controller divide into different functional blocks are connected through the signal state of line, and the associated modules control the whole process through state machine. In addition, in order to improve the speed of the SDRAM buffer, select work mode under the SDRAM page burst.As a result, the speed of SDRAM read and write improved dramatically. The whole control system through simulation and online logic analyzer demonstrate that: SDRAM controller can read and write control accurately, stable and reliable, and it can be applied to different speeding cache systems.

Abstract: Negative-bias temperature instability(NBTI)is a major challenge for modern integrated circuits manufacture In this paper,We discuss the results of such stress on device and circuit Performance NBTI is approached from a process point of view,providing a general picture of the manufacturing process steps that affect NBTI performance It is found that several process steps may be optimized to reduce the NBTI suscepti-bility of p-type MOSFETs

Abstract: A set of SoC low power design methods is presented and used to different level of A SoC, such as system level, IP module level and RTL level. In system level operating mode is considered, in module level software management is considered and in RTL level gating clock is considered. Power simulation results show that the static and dynamic power of the SoC is quite low. The goals of the low power design methods applied on the design are achieved. The SoC has been implemented in 0.18μm CMOS process, the area is 7.8 mm×7.8 mm , the operation frequency is 80 MHz and the power dissipation is about 454.268 mW.