Institution
LogicVision
About: LogicVision is a based out in . It is known for research contribution in the topics: Fault coverage & Automatic test pattern generation. The organization has 56 authors who have published 116 publications receiving 4799 citations.
Topics: Fault coverage, Automatic test pattern generation, Jitter, Clock domain crossing, Synchronous circuit
Papers published on a yearly basis
Papers
18 Oct 1998
TL;DR: An overview of current industrial practices as well as academic research in core-based IC design is provided and the challenges for future research are described.
Abstract: Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.
527 citations
28 Sep 1999
TL;DR: This paper provides a preliminary, unapproved view on IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language.
Abstract: Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.
167 citations
3 Nov 1997
TL;DR: An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise and is particularly suitable for sigma-delta converters.
Abstract: An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to be implemented as a built-in self-test for an IC, and is particularly suitable for sigma-delta converters.
162 citations
28 Sep 1999
TL;DR: This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL).
Abstract: Phase-locked loops (PLLs) are an essential building block of most digital and mixed-signal ICs. This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL). The parameters tested include lock range, lock time, RMS jitter, and loop gain (from which the natural frequency is calculated). Experimental waveforms and results are shown for a 200 MHz PLL which uses a phase-frequency detector. Test time is typically 10 ms, much faster than for conventional testing.
147 citations
TL;DR: In this article, the development of fault-finding circuits built into ICs which will disclose defects in today's and tomorrow's block-based designs are examined, as well as their application in fault detection.
Abstract: Developments in fault-finding circuits built into ICs which will disclose defects in today's and tomorrow's block-based designs are examined.
123 citations
Authors
Showing all 56 results
| Name | H-index | Papers | Citations |
|---|---|---|---|
| Yervant Zorian | 35 | 85 | 4794 |
| Stephen Sunter | 28 | 85 | 2220 |
| Benoit Nadeau-Dostie | 17 | 24 | 842 |
| Benoit Nadeau-Dostie | 14 | 32 | 565 |
| A. Roy | 13 | 17 | 653 |
| Jean-Francois Cote | 12 | 14 | 544 |
| Naveena Nagi | 11 | 17 | 715 |
| Jean-Francois Cote | 11 | 19 | 378 |
| Fadi Maamari | 5 | 6 | 98 |
| J.-F. Cote | 5 | 5 | 155 |
| Dwayne Burek | 4 | 4 | 119 |
| Paul Price | 4 | 5 | 124 |
| Sonny Ngai San Shum | 3 | 3 | 38 |
| Givargis A. Danialy | 3 | 4 | 88 |
| Pierre Gauthier | 3 | 3 | 73 |
Related Institutes (5)
Performance Metrics
| Year | Papers |
|---|---|
| 2025 | 1 |
| 2024 | 1 |
| 2023 | 3 |
| 2009 | 3 |
| 2008 | 2 |
| 2007 | 4 |