Civilian Marksmanship Program

Abstract: Process variations complicate at-speed testing enormously. Different paths have different sensitivity signatures, and therefore each chip can potentially have a different critical path depending on the manufacturing parameters of that chip. This presentation will discuss how process variations can systematically be covered by exploiting statistical timing to select paths for at-speed structural test. Simultaneous coverage of process variations and satisfaction of sensitization conditions will be discussed. Due to increasing process variability in modern technologies, selection of optimal test margins is important to reduce pessimism while ensuring quality of shipped chips. Use of binning techniques to increase yield in the face of wide process variations is becoming more prevalent. Timing closure, margining and testing for binned chips can also take advantage of statistical timing to improve yield and quality.