System-Level Interconnect Prediction 

Abstract: Interconnect has become a primary bottleneck in integrated circuit design As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies Electrical and optical interconnects are compared for various design criteria based on these predictions The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node

Abstract: In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.

Abstract: The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more than 20% and a via reduction of more 30%. Because of the rapidly increasing percentage of delay due to interconnect and the manufacturing challenges due to vias in the nanometer realm, these length and via reductions result simultaneously in a chip performance improvement of 10%, a power reduction of 20%, and a die cost reduction of 30%. Furthermore, the reduction in both wire length and parallel runs on different layers often both reduces die size and improves signal integrity. Remarkably, on virtually every important measure of chip quality, the X Architecture is superior to the Manhattan architecture.While diagonal wiring has been discussed for years, and short diagonal jogs have even been used for years, pervasive diagonal wiring has not been used on an IC before 2002 (to our knowledge). The fundamental reasons for this are not manufacturing limitations, as might be suspected, but EDA limitations, and the changes required to take full advantage of the X Architecture are significant and numerous. In particular, routing must be not only octilinear, but also gridless and non-preferred direction. In addition, significant changes are required at least in floorplanning, placement, global routing, extraction, power routing, clock routing, wire length estimation (e.g., in synthesis), database, graphics, and even data interchange formats. The folklore that 45-degree wiring might not be worth the trouble because it can provide only a 10% reduction in wire length is rooted in the incorrect assumptions that (a) only the router must change, (b) the router must resemble contemporary, preferred-direction, net-at-a-time maze routers, and (c) that wire length is the only major contributor to interconnect delay.In this short paper, we present some of the challenges and opportunities afforded by the X Architecture and show some early results that demonstrate the promise of pervasive, diagonal wiring, reflecting our belief that five years from now, virtually all, high-performance, integrated circuits will use the X Architecture.

Abstract: Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recent advances in integrated optical devices may deliver alternative interconnect solutions enabling drastically enhanced performance. This paper begins by outlining some of the more pressing issues in interconnect design, and goes on to describe system-level optical interconnect for inter- and intra-chip applications. Inter-chip optical interconnect, now a relatively mature technology, can enable greater connectivity for parallel computing for example through the use of optical I/O pads and wavelength division multiplexing. Intra-chip optical interconnect, technologically challenging and requiring new design methods, is presented through a proposal for heterogeneous integration of a photonic "above-IC" layer followed by a design methodology for on-chip optical links. Design technology issues are highlighted and the paper concludes with examples of the use of optical links in clock distribution (with quantitative comparisons of dissipated power between electrical and optical clock distribution networks) and for novel network on chip architectures.