NORCHIP 

Abstract: In recent years, there have been major advances in integrated circuit technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signal. Such circuits, called multiple-valued logic circuits, offer several potential opportunities for the improvement of present VLSI circuit designs. In this paper, we give an overview of recent developments in multiple-valued logic circuit design, revealing both the opportunities they offer and the challenges they

Abstract: This paper presents hardware implementations of Taylor series. The focus will be on the exponential function but the methodology is applicable on any unary function. Two different architectures are investigated, one, original, straight forward and one modified structure. The outcomes are higher performance, lower area, and lower power consumption for the modified architecture compared to the original.

Abstract: Quantum-dot Cellular Automata (QCA) is a promising successor for CMOS transistor technology, while allowing the implementation of logic circuits using quantum devices, such as quantum dots or single domain nano magnets, a new set of tools must be developed to assist the design and implementation process. Examples of such tools are the QCADesigner for handmade layout and physical simulation, and also tools for majority logic optimization. Since no tool is available for assisting the QCA layout generation, we propose tool to automatically generate the layout of QCA circuits. This tool, designated by QCA-Layout Generator (QCA-LG), was integrated in a general QCA technology design flow, accepting the most used formats of the synthesis tools and producing the layout output according to the QCADesigner tool. Therefore, the layout of a logical circuit described in VHDL is automatically generated, and can be further optimized by hand and simulated using the QCADesigner. Examples of layouts automatic generated by the QCA-LG are presented for simple logical circuits, and are also compared with optimal layouts designed by hand.

Abstract: This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 μm 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.