Conference
Non-Volatile Memory Technology Symposium
About: Non-Volatile Memory Technology Symposium is an academic conference. The conference publishes majorly in the area(s): Non-volatile memory & Resistive random-access memory. Over the lifetime, 314 publications have been published by the conference receiving 2146 citations.
Papers
30 Dec 2008
TL;DR: In this paper, the resistance change memory element is formed by a conductive metal oxide adjacent to an oxide tunnel barrier, where the barrier height varies due to changes in charge within the barrier as a result of oxygen ions moving in or out of the tunnel barrier.
Abstract: We report a dual oxide layer as the active memory element of a scalable nonvolatile cross-point memory technology. The resistance change memory element is formed by a conductive metal oxide adjacent to an oxide tunnel barrier. Varying the as-deposited tunnel barrier thickness allows for control of the nominal current density and is targeted to meet the cell requirements for an ultra high density cross-point architecture. Excellent scaling of program and erase currents with electrode area and a continuous transition between program and erase state indicate that a uniform rather than a filamentary switching mechanism controls the device current both in the high and the low resistive state. A prior forming step is not required. The observed resistance change is caused by the exchange of oxygen ions between the conductive metal oxide and the tunnel oxide. Ion motion at room temperature is enabled by an exponential increase of the ion mobility under high electric fields during program and erase operations. The resistive switching effect of the device is explained by a change in the tunneling current due to an increase or decrease in effective tunnel barrier height. The barrier height varies due to changes in charge within the barrier as a result of oxygen ions moving in to or out of the tunnel barrier.
178 citations
1 Oct 2016
TL;DR: In this paper, potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed, based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectricinsulator- semiconductor gate stack are the dominant degradation mechanisms during program and erase operation.
Abstract: In this paper potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed. These pathways are based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectricinsulator- semiconductor gate stack are the dominant degradation mechanisms during program and erase operation. Three different approaches capable of lowering or eliminating the interfacial field stress are being assessed - lowering the electrical field stress induced by polarization reversal; utilizing low voltage sub-loop operation; altering the capacitive divider within the gate stack.
99 citations
1 Oct 2009
TL;DR: In this paper, the authors proposed a phase change memory (PCM) based NVRAM with optimized process integration and cell programming to support data retention to 10 years at 85 °C and greater than 106 write cycles.
Abstract: Phase Change Memory (PCM) has emerged as an attractive candidate for next-generation non-volatile memory devices. For these applications, reliability is determined by the ability to retain the state of data in the device and support a specified number of re-writes without failure. In PCM technologies, retention is limited by the meta-stable amorphous state of the cell. For cycling endurance (re-writes), failure occurs due to either void formation in the active material or contamination of the heating element of the cell. With optimized process integration and cell programming, large array devices based on a 90nm PCM technology are able to support data retention to 10 years at 85 °C and greater than 106 write cycles.
79 citations
1 Nov 2006
TL;DR: In this paper, NiSi electrically programmable fuses (eFUSE) were fabricated and investigated using 65 nm logic CMOS technology and the optimization of fuse program was achieved by analyzing electrical and physical responses of fuse bits for various conditions.
Abstract: NiSi electrically programmable fuses (eFUSE) were fabricated and investigated using 65 nm logic CMOS technology. The optimization of fuse program was achieved by analyzing electrical and physical responses of fuse bits for various conditions. Controlled electromigration of Ni during fuse program was identified as a key factor in achieving reliably high post-program fuse resistance.
60 citations
26 Dec 2007
TL;DR: In this paper, the authors present the results on resistive switching in Ag/Ag-Ge-Se/Pt cells which can show a resistance ratio of more than 5 orders of magnitude.
Abstract: Solid electrolytes such as Agy(GexSe1-x)1-y allow rapid diffusion of metal ions and this makes them suitable for memory applications. The switching mechanism in these materials is based on cation migration from an oxidizable electrode (e.g., Ag) under positive bias and the reduction of the metal ions at the counter electrode (e.g., Pt). A metallic connection forms between the electrodes which is stable when the voltage is switched off but can be dissolved when the voltage polarity is reversed. We present our results on resistive switching in Ag/Ag-Ge-Se/Pt cells which can show a resistance ratio of more than 5 orders of magnitude. The ON resistance depends on the write current which allows for multi-bit data storage. The leakage current in the high resistance state can significantly be reduced by introducing an oxide layer within the chalcogenide film. Then, a current as low as 1 nA is sufficient to switch these cells from a high to a low resistance state demonstrating the possibility of extremely low power consumption.
59 citations
Performance Metrics
| Year | Papers |
|---|---|
| 2019 | 10 |
| 2018 | 16 |
| 2017 | 15 |
| 2016 | 9 |
| 2015 | 37 |
| 2014 | 36 |