IEEE Multi-Chip Module Conference 

Abstract: The authors evaluate a prototype silicon-on-silicon multichip module for potential use in cost-driven applications. The incorporation of integrated passive components, resistors and capacitors, in the module substrate is a significant advantage in many of these kinds of applications. A module has been built that incorporates both linear and bipolar and digital CMOS circuits. The unique features of the module are discussed, as well as the properties and performance limits of the resulting passive components. >

Abstract: With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new /spl Pi/ model for distributed RC and RLC interconnects to estimate the driving point admittance at the output of a CMOS gate. Using this model we are able to compute the gate delay efficiently, within 25% of SPICE-computed delays. Our parameters depend only on total interconnect tree resistance and capacitance at the output of the gate, Previous "effective load capacitance" methods, applicable only for distributed RC interconnects, are based on /spl Pi/ model parameters obtained via a recursive admittance moment computation. Our model should be useful for iterative optimization of performance-driven routing or for estimation of gate delay and rise times in high-level synthesis.

Abstract: A multichip module technology in which the module's power planes cover the entire module surface and are separated by 0.15- mu m of anodized aluminum (Al/sub 2/O/sub 3/) is discussed. The module provides 50 nF/cm/sup 2/ decoupling capacitance across the power supply planes with negligible series inductance. The large capacitance eliminates the need for most if not all discrete capacitors, thereby saving space, reducing delays and increasing packing density. The negligible inductance yields modules having less inductive voltage drop between power levels than any equivalent module relying on discrete decoupling capacitors. >

Abstract: This paper presents a sensitivity-based wiresizing algorithm for interconnect delay optimization of lossy transmission line topology under MCM technologies. Our approach computes the maximum delay and its sensitivities with respect to the widths of wires in the topology via high order moments based on an exact moment matching model. Compared with other approaches, it achieves analytical sensitivity computation and calculates higher order moments (sensitivities) recursively from lower order moments for tree network. It can yield optimal wiresizing solution for interconnect delay minimization. Experiments show that the delay estimation using high order moments is very accurate compared with SPICE simulation and our approach can reduce the maximum rising delay by over 60% with small penalty in routing area. Besides delay optimization, the final solution eliminates the over-shoot of response waveform and is robust under parameter variations.