In this work, we exploit a 2TnC ferroelectric random access memory (FeRAM) cell design to realize the quasi-nondestructive readout (QNRO) of ferroelectric polarization ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P FE ) in a capacitor, which can relax the endurance requirement of the ferroelectric thin film and exploits the benefits of both FeRAM and ferroelectric FET (FeFET). We demonstrate that: i) QNRO sensing of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P FE is conducted successfully in experiment with a ON/OFF ratio ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I ON / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I OFF )>10 3 , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I ON >10 μA, and read endurance>10 6 cycles, which can relax the FeRAM endurance requirement by 10 6 x; ii) optimization of the cell performance can be realized by tuning the metal-ferroelectric-metal capacitor (MFM) capacitor to read transistor area ratio and read transistor threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V TH ); iii) the 2TnC cell structure is 3D-compatible, enabling integration of highly dense memory solution; iv) the 2TnC cell structure also enables compute-in-memory (CIM) applications of FeRAM, which has not been widely explored. With this technology, storage and memory-centric computing can be enabled.

Quasi-Nondestructive Read Out of Ferroelectric Capacitor Polarization by Exploiting a 2TnC Cell to Relax the Endurance Requirement

Seed layer engineering in ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) film has been investigated systematically in this work. Among four kinds of seed layers (ZrO2, HfO2, Al2O3, and TiO2), the HZO capacitor with TiO2 seed layer achieves preferable performance (larger Pr, smaller Ec, and nearly wakeup-free). It is considered that the suppression of interfacial defects by seed layers could be a key for wakeup-free achievement. For further understanding, with reliability characterizations and theoretical calculations, it is found that defects (oxygen vacancy <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {O}}^{+}$ </tex-math></inline-formula>) generation at the TiN/HZO interface and their migration into inner film could be dominant reasons for the leakage and Pr degradation in cycling, while <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {O}}^{+}$ </tex-math></inline-formula> at the TiO2/TiN interface can attribute to the imprint effect. Thereby, a novel asymmetric stress field cycling (ASFC) scheme is proposed to suppress Pr fatigue by keeping defects at one-side interface rather than migrating into the inner film.

In-Depth Investigation of Seed Layer Engineering in Ferroelectric Hf$_{\text{0.5}}$Zr$_{\text{0.5}}$OTEXPRESERVE2 Film: Wakeup-Free Achievement and Reliability Mechanisms

Ferroelectric FET (FeFET) is a singularly attractive emerging technology with a rich feature set. Boasting high versatility, it has already been implemented in a host of applications, like dense memory arrays and in-memory computing (IMC). Nevertheless, being an emerging technology, FeFETs are faced with reliability concerns that warrant analysis and mitigation. As a first step, modeling the FeFET variability can help to ascertain its present applicability. For instance, binary neural networks (BNNs) are more error resilient than classical deep-neural networks implementations and thus, can utilize this emerging yet unreliable hardware. However, conventional machine learning (ML) still relies on large datasets for training that need to be processed many times by the algorithm, exposing the memory wall of the von Neumann architecture. This necessitates the pursuit of new computing paradigms, like hyperdimensional computing (HDC). HDC is an emerging brain-inspired ML algorithm that can learn from very little data, using pattern recognition and randomness as its core working principles. Thus, it is inherently robust against noise and errors in the employed computing hardware. Hence, the robust HDC and the efficient yet unreliable FeFET are fiercely symbiotic. In this work, we will cover the challenges of the emerging FeFET technology and how to model them on a device level. We will then make use of these models and inject them into applications to study their error resiliency. For this, we will use the aforementioned applications of BNNs and HDC, and showcase their response to the unreliable hardware.

FeFET Reliability Modeling for In-Memory Computing: Challenges, Perspective, and Emerging Trends

The recent discovery of ferroelectricity in pure ZrO2 has drawn much attention, but the information storage and processing performances of ferroelectric ZrO2-based nonvolatile devices remain open for further exploration. Here, a ZrO2 (∼8 nm)-based ferroelectric capacitor using RuO2 oxide electrodes is fabricated, and the ferroelectric orthorhombic phase evolution under electric field cycling is studied. A ferroelectric remnant polarization (2Pr) of >30 μC/cm2, leakage current density of ∼2.79 × 10-8 A/cm2 at 1 MV/cm, and estimated polarization retention of >10 years are achieved. When the ferroelectric capacitor is connected with a transistor, a memory window of ∼0.8 V and eight distinct states can be obtained in such a ferroelectric field-effect transistor (FeFET). Through the conductance manipulation of the FeFET, a high object image recognition accuracy of ∼93.32% is achieved on the basis of the CIFAR-10 dataset in the convolutional neural network (CNN) simulation, which is close to the result of ∼94.20% obtained by floating-point-based CNN software. These results demonstrate the potential of ferroelectric ZrO2 devices for nonvolatile memory and artificial neural network computing.

Pure ZrO2 Ferroelectric Thin Film for Nonvolatile Memory and Neural Network Computing.

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string. 

A Novel 3D 2TnC FeRAM Architecture and Operation Scheme with Improved Disturbance for High-Bit-Density Dynamic Random-Access Memory

In this work, a thorough assessment of the robustness of complementary channel HfO2 ferroelectric FET (FeFET) against total ionizing dose (TID) radiation is conducted, with the goal of determining its suitability for use as high-performance and energy-eﬃcient embedded nonvolatile memory (eNVM) for space applications. We demonstrate that: i) ferroelectric HfO2 thin ﬁlm is robust against X-ray and proton irradiation; ii) FeFET exhibits a polarization state dependent radiation sensitivity where the high-VTH (HVT) state sees noticeable negative VTH shift and low-VTH (LVT) is immune to irradiation, irrespective of the channel type; iii) the state dependence is ascribed to the depolarization ﬁeld in

Evaluating the Robustness of Complementary Channel Ferroelectric FETs Against Total Ionizing Dose Towards Radiation-Tolerant Embedded Nonvolatile Memory

In this work, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

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Papers

Quasi-Nondestructive Read Out of Ferroelectric Capacitor Polarization by Exploiting a 2TnC Cell to Relax the Endurance Requirement

Evaluating the Robustness of Complementary Channel Ferroelectric FETs Against Total Ionizing Dose Towards Radiation-Tolerant Embedded Nonvolatile Memory

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications