Zhouhang Jiang
University of Electronic Science and Technology of China
18 Papers
Zhouhang Jiang is an academic researcher from University of Electronic Science and Technology of China. The author has contributed to research in topics: Computer science & Engineering. The author has an hindex of 1, co-authored 1 publications.
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Papers
A new series of low-loss multicomponent oxide microwave dielectrics with a rock salt structure: Li5MgABO8 (A=Ti, Sn; B=Nb, Ta)
Xing Zhang,Zhouhang Jiang,Bin Tang,Zixuan Fang,Zixuan Fang,Zhe Xiong,Hao Li,C. L. Yuan,Shuren Zhang +8 more
TL;DR: In this article, a series of Li5MgABO8 (A=Ti, Sn; B=Nb, Ta) compounds were designed and synthesized through a solid-state reaction method.
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Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window
Zhouhang Jiang,Yi Xiao,Swetaki Chatterjee,Halid Mulaosmanovic,S. Duenkel,Steven R. Soss,Sven Beyer,Rajiv V. Joshi,Yogesh Singh Chauhan,Hussam Amrouch,N. Vijaykrishnan,Kai Ni +11 more
- 12 Jun 2022
TL;DR: In this article , the asymmetric double-gate concept was applied to decouple the tradeoff between ferroelectric (FE) thickness scaling and memory window reduction in FeFETs.
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On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond
Yi Xiao,Yixin Xu,Zhouhang Jiang,Shan Deng,Zijian Zhao,Antik Mallick,Limeng Sun,Rajiv V. Joshi,Xueqing Li,Nikhil Shukla,Vijaykrishnan Narayanan,Kai Ni +11 more
- 03 Dec 2022
TL;DR: In this paper , a comprehensive model which reflects two FeFET write mechanisms was proposed, one to ground Source (S), Drain (D) & Body (B) nodes and use Gate (G) to write, and the other to float S/D and use G & B to write.
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Ferroelectric compute-in-memory annealer for combinatorial optimization problems
Xunzhao Yin,Yu Qian,Alptekin Vardar,Marcel Günther,F. Müller,N. Laleni,Zijian Zhao,Zhouhang Jiang,Zhiguo Shi,Yiyu Shi,Cheng Zhuo,Thomas Kämpfe,Kai Ni +12 more
TL;DR: Researchers developed a ferroelectric compute-in-memory annealer for efficiently solving large-scale combinatorial optimization problems, achieving 75% chip size reduction and 2X speedup, with potential for solving general COPs using a 28nm HKMG CMOS technology.
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Charge trapping challenges of CMOS embedded complementary FeFETs
Sven Beyer,Dominik Kleimaier,Stefan Dipl.-Ing. Dünkel,Halid Mulaosmanovic,S. Soss,Zhouhang Jiang,Kai Ni,Thomas Mikolajick,Haidi Zhou +8 more
- 12 May 2024
TL;DR: Charge trapping challenges of CMOS embedded complementary FeFETs involve polarization switching, interface trapped charge accumulation, and the sloshing bathtub model.
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