Elliptic curve-based cryptography (ECC) has become the automatic choice for public key cryptography due to its lightweightness compared to Rivest–Shamir–Adleman (RSA). The most important operation in ECC is elliptic curve scalar multiplication, and its efficient implementation has gathered significant attention in the research community. Fast implementation of ECC scalar multiplication is often desired for speed-critical applications such as runtime authentication in automated cars, web server certification, and so on. Such fast architectures are achieved by implementing ECC scalar multiplication in fields with pseudo-Mersenne prime or Solinas prime. In this paper, we aim to implement a fast implementation of ECC scalar multiplication for any generic Montgomery curve in Galois Field in p [GF(p)] without having the constraint of using any specialized modulus. We will show that the proposed ECC scalar multiplication architecture is as fast as scalar multiplication in special curves like Curve25519, albeit with little area overhead. The proposed architecture can be modified to support ECC scalar multiplication in both Montgomery and short Weierstrass curves.

High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves

Nowadays, diagnosing patient diseases remotely is a routine and digital medical images analysis as a part of Telecare Medical Information Systems (TMIS) play a fundamental role in early diagnosing and treating most common and serious diseases such as breast cancer. In this context, altering or distorting even a single pixel of a medical image during its transmission over an unsure channel could lead to a wrong diagnosis and harm patient health, induce damaging delays. Therefore the security and privacy of the transmitted medical images must be addressed most seriously. Several techniques are proposed in the literature to address these issues using different techniques such as chaos theory, more recently, elliptic curves cryptography (ECC) or improved classical methods such as linear cryptography. In this paper, we address the security level concern of an image encryption technique combining ECC with Hill cipher (ECCHC) which has been recently proposed by Dawahdeh et al [13]. Our study rises concerns about some weaknesses and flaws of the analyzed encryption scheme against some plain-text and known plain-text attacks. In addition, and not least issue, it is found that the key length used in Dawahdeh et al. scheme is not sufficiently large to be robust against brute force attack. To fix the found flaws and to improve the encryption scheme, a generalized cryptosystem is suggested. In the enhanced version, the key matrix negotiation is redefined to a cipher that combines a modified EC Integrated Encryption Scheme (ECIES) and the linear multiplication matrix is generalized to key matrix of (2n × 2n), n > 2 to counter efficiently the exhaustive search attack. The effectiveness of the proposed version is evaluated and verified through extensive experimentation and most recent available security tools. Compared with the state-of-the art techniques, the proposed version exhibits excellent security features and can resist to various knowing attacks.

An efficient image encryption scheme for TMIS based on elliptic curve integrated encryption and linear cryptography

This brief presents an energy-efficient elliptic curve cryptography (ECC) processor for Internet of Things (IoT) security applications. The proposed processor supports dual-field computations, and employs various design techniques across the algorithm, architecture, and arithmetic circuit levels to minimize power and energy consumption. The proposed elliptic curve point multiplication (ECPM) algorithm employs signed binary representation (SBR) with the m-ary method to reduce both area and energy consumption, while avoiding attack from simple power analysis (SPA). In addition, the proposed hybrid modular arithmetic architecture effectively increases the hardware utilization to reduce both area and energy cost. Finally, the proposed processor uses an energy-efficient data flow to further minimize memory overhead for group operations. The proposed ECC processor achieves 51.6% and 50.5% lower energy consumption for each $GF(p)$ and $GF(2^{m})$ ECPM operation, respectively, when compared to state-of-the-art ECC designs.

An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications

The summation of multiple operands in parallel forms part of the critical path in various digital signal processing units To speedup the summation, high compression ratio counters and compressors are necessary In this article, we present a novel method of fast saturated binary counters and exact/approximate (4:2) compressors based on the sorting network The inputs of the counter are asymmetrically divided into two groups and fed into sorting networks to generate reordered sequences, which can be solely represented by one-hot code sequences Between the reordered sequence and the one-hot code sequence, three special Boolean equations are established, which can significantly simplify the output Boolean expressions of the counter Using the above method, we construct and further optimize the (7,3) counter that can perform 270%, 262%, and 520% better in maximum than other designs in delay, area–delay product, and power–delay product, respectively Similarly, the (15,4) counter is constructed, and it achieves approximately 353% shorter delay, while it significantly consumes less power and area The constructed (31,5) counter has approximately 267% higher performance with the area increasing instead When the counters are embedded in a $16\times 16$ bit multiplier, the performance of the multiplier in area delay product and power delay product is 318% and 321% higher than that embedded in other counter designs, respectively Besides, we also construct exact/approximate (4:2) compressors based on sorting network, and they are 102%–374% better in the area–delay product and 223%–480% better in power–delay product when they are embedded in an $8\times 8$ bit approximate multiplier

Fast Binary Counters and Compressors Generated by Sorting Network

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

https://www.mdpi.com/1424-8220/21/4/1451/pdf

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA.

In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom–Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 $\mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $\mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works.

High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication

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High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication