This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 μA 7-20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240-500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 μm CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 μA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/√ Hz IRN density, and occupies 0.21 mm 2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/√ Hz IRN density, and occupies 0.23 mm 2 silicon area without pads.

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps

This paper presents a fully integrated low-power 130-nm CMOS transceiver tailored to the Bluetooth low energy (BLE) standard. The receiver employs a passive front-end zero-IF architecture, which is directly driven by a quadrature voltage-controlled oscillator (QVCO) without any buffering stage. The QVCO, embedded in a fractional- $N$ phase-locked loop (PLL), employs a passive $RC$ network to cancel the parasitic magnetic coupling between the two cores so as to keep the quadrature phase error below 1.5 $^{\circ}$ . The PLL exhibits a high loop bandwidth of 1 MHz to sufficiently reduce the frequency pulling effects due to close-by interferers. The transmitter uses a direct-modulation Gaussian frequency-shift keying scheme in which small PMOS-based cells modulate the output signal of one of the cores of the QVCO. In the baseband section, the transceiver employs a 4-bit phase-domain ADC based on novel linear-combiner topology to generate the required phase rotations. The proposed combiner operates in current domain and does not employ resistors, leading to a power- and area-efficient demodulator implementation. The complete receiver achieves a sensitivity of ${-}$ 81.4 dBm and fulfills the BLE requirements on interference blocking. It consumes 1.1 mW from a 1.0-V supply and has a similar power efficiency as recent super-regenerative receivers that are much more susceptible to interferers. The transmitter delivers 1.6-dBm output power to a differential 100 $\Omega$ and consumes 5.9 mW, which implies a total efficiency of 24.5%.

A 1.1-mW-RX ${-}{\hbox{81.4}}$ -dBm Sensitivity CMOS Transceiver for Bluetooth Low Energy

In this work, we implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver using various low-power techniques for low-rate wireless personal area network (IEEE 802.15.4 LR_WPAN) applications in 0.18-μm CMOS technology. In order to achieve an ultra low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are all implemented in this transceiver. The transmitter achieves less than 5.0% error vector magnitude (EVM) at 5 dBm output, and the receiver sensitivity is -101 dBm. The sensitivity of the wake-up block is -29.8 dBm. The current consumption is below 14.3 mA for the data receiving mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V power supply. That is considered to be lowest for the 2.4 GHz CMOS ZigBee transceiver compared to open literature results.

An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and a low-pass filter (LPF). It consists of the cascade of three biquadratic cells made up by opamps in a series-shunt configuration, which features high input impedance, low load effects in the cascade blocks, and better frequency response. The opamp parameters are included in the overall biquad transfer function. This allows getting very low power performance, since the opamp bandwidth is not required to be much larger than the filter cutoff frequency. Moreover, the current consumption is optimized according to the selected gain level (1.3 mA at 0 dB-gain up to 1.9 mA at 40 dB-gain). The PGA features a 0-40 dB programmable gain range with a 5 dB gain-step. The LPF performs a sixth-order 255 MHz low-pass frequency response. For the overall chain the IIP3 is 14 dBm at 0 dB gain, while the input referred noise is 12.5 nV/√Hz at 40 dB gain.

A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers

This paper demonstrates a highly integrated transceiver for 802.15.4, consuming a dc power of 18 mW and 22.3 mW in the Tx and Rx mode respectively. The g m boosted LNA shares the dc current with mixer, complex filter uses transistorized biquads, Limiting Amplifier and RSSI chain uses two local loops to save dc power. In the Tx, 2-point direct FSK modulation using normal sized varactors are used in the PLL, which not only obviates the need for auto calibration but also saves dc power due to the absence of DAC. The low IF receiver achieves a sensitivity of −94 dBm, an over load point of −20 dBm adjacent and alternate channel rejections of 40 dB and 55 dB respectively and a linear RSSI range of 89 dB. The transmitter delivers an OQPSK modulated signal of 0 dBm, with an EVM of 7% and the output spectrum meets the mask requirements of 802.15.4, FCC & ETSI. Implemented in 0.18-µm CMOS, loop filter and the crystal resonator for the PLL are the only external components apart from the decoupling capacitors.

A 18 mW Tx, 22 mW Rx transceiver for 2.45 GHz IEEE 802.15.4 WPAN in 0.18-µm CMOS

This paper presents a fully integrated low cost, low noise 10GHz synthesizer using 65nm RF CMOS process. The synthesizer provide low phase-noise and low reference spur, covering 8.3GHz to 11.3GHz using multiband low gain VCO with auto calibration for locking. The measured phase-noise of 9.75GHz is −77dBc/Hz at lKHz offset, −90.1dBc/Hz at 10KHz offset, −98.6dBc/Hz at 100KHz offset, and −112.5dBc/Hz at 1MHz offset, phase RMS jitter performance is to be less than 1.1° integrated from lKHz to 1MHz, while maintaining 26MHz reference spur levels lowers −74.6dB cover the entire tuning range. The active die area is 0.55mm × 0.8mm. The chip operates over a wide range of supply voltage from 1.1 V to 1.3V and temperature from −40°C to +85°C respectively. The chip draws 31mA current with buffer from a +1.2V supply at +25°C.

A 8.3–11.3GHz low cost integer-N synthesizer with 1.1° RMS phase error in 65nm CMOS

A low noise, 250-MHz fifth order 0.1 dB ripple chebyshev g m -C filter, with a novel discrete tuning scheme is presented. The discrete tuning circuit switches ON/OFF small g m cells which are connected in parallel to the main g m cell, based on the PVT conditions, to correct for the shift in the cutoff frequency f c . Compared to conventional tuning schemes, proposed discrete scheme demonstrates improved performance in terms of noise and optimal voltage swing across PVT. The chip was fabricated in standard 0.18-μm CMOS technology. Measured results show a f c of 245 MHz, equivalent input noise voltage of 166 μV, IIP3 of −2.5 dBV in pass band and 2.5 dBV in stop band, Input referred P1dB of −6.6 dBV, IIP2 of 55 dBV, consuming 19 mA from 1.8 V supply. The tuning circuit, in combination with a PTAT bias, maintains the bandwidth within ±5% of nominal f c of 250 MHz for VDD variation of 1.8±0.1V and temperature variation of −40°C to 85°C.

A 250-MHz g m -C filter with discrete tuning scheme in 0.18-μm CMOS for UWB receiver

This paper presents a fully integrated low power, low noise 400MHz fractional-N with direct modulation using 0.13μm CMOS process. The synthesizer provide low phase-noise, covering 410MHz to 490MHz using multiband low gain VCO, Direct modulation that supports three data rate viz, 4.8Kbps, 2.4Kbps and 1.2Kbps GFSK and GMSK. The measurement result show the phase-noise of is −101dBc/Hz at 10KHz offset and −126dBc/Hz at 1MHz offset at 420MHz. The active die area is 0.55mm × 0.8mm. The chip operates over a wide range of supply voltage from 1.2 to 1.5V and temperature from −40°C to +85°C respectively. The chip draws 3.95mA current with divide by 2 and buffer from a +1.2V supply at +25oC.

A 400MHz low power fractional-N synthesizer with GFSK/GMSK modulation in 0.13μm CMOS

A low noise, 250-MHz fifth order 01 dB ripple chebyshev Gm-C filter, with a discrete tuning scheme in 018-μm CMOS is presented The tuning circuit employs an amplitude locked loop (ALL) to find the correct tuning word to maintain fc within 250MHz ±5% for VDD variation of 18±01V, temperature variation of -40°C to 125°C and across process corners Compared to conventional tuning schemes, proposed discrete scheme demonstrates lower input referred noise of 113 nV/√Hz with tighter bandwidth accuracy and consistent performance across PVT Analysis of Gm cell non-idealities such as ro and Cdg on filter response to ensure optimum design is another contribution of this paper

Analysis and design of a 250-MHz Gm-C filter with discrete tuning scheme in 0.18-μm CMOS for UWB receiver

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