This paper proposes a new systolic array architecture to perform division operations over GF(2m) based on the modified Stein’s algorithm. The systolic structure is extracted by applying a regular approach to the division algorithm. This approach starts by obtaining the dependency graph for the intended algorithm and assigning a time value to each node in the dependency graph using a scheduling function and ends by projecting several nodes of the dependency graph to a processing element to constitute the systolic array. The obtained design structure has the advantage of reducing the number of flip-flops required to store the intermediate variables of the algorithm and hence reduces the total gate counts to a large extent compared to the other related designs. The analytical results show that the proposed design outperforms the related designs in terms of area (at least 32% reduction in area) and speed (at least 60% reduction in the total computation time) and has the lowest AT complexity that ranges from 80% to 94%.

New systolic array architecture for finite field division

Signal processing techniques and applications

Unified systolic array architecture for finite field multiplication and inversion

Scalable digit-serial processor array architecture for finite field division

Modular multiplication and inversion are the essential operations in many Public Key Cryptosystems (PKCs). In this paper, we describe a unified digit-serial inverter/multiplier in GF(2m). The inversion is based on a modified Extended Euclidean Algorithm (EEA), while the multiplication is based a LSB-first multiplication algorithm. As the inverter and multiplier share the data-path, it is smaller than Arithmetic Logic Units (ALUs) with separated inverters and multipliers. When choosing digit size to be w, this inverter/multiplier finishes one inversion and one multiplication in [2m-1/w] and [m/w] clock cycles, respectively.

A digit-serial architecture for inversion and multiplication in GF(2 M )

We propose in-place systolic bit-serial, bit-parallel, and folded bit-parallel architectures for inversion in GF(2m). Our bit-serial architectures have the highest throughput 1/m of the three types but use more hardware than the other two types. Our bit-parallel architectures have throughput of 1/(2m − 1) with interleaved inputs and 1/(4m − 2) without interleaving. The new bit-serial and bit-parallel architectures proposed have the same throughput and latency but smaller hardware cost and shorter critical path delay than the best comparable architectures proposed previously. We also propose novel folded versions of our bit-parallel architectures which achieve 1/(4m − 2) non-interleaved throughput with even less hardware than our bit-parallel architectures. To the best of our knowledge, no comparable scheme has been proposed previously. The circuitry in each cell of our bit-serial architectures and the (folded and unfolded) bit-parallel architectures with distributed ring counters is the same for all values of m. Since there are no global control or data signals either, these architectures have excellent scalability properties and are very suitable for applications where m is large or variable. Implementation details using the TSMC Avanti 0.18 µm CMOS standard cell library are provided.

http://ieeexplore.ieee.org/iel5/10348/32912/01541357.pdf

Hardware-efficient systolic architectures for inversion in GF(2/sup 2/)

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Hardware-efficient systolic architectures for inversion in GF(2/sup 2/)