Yutaka Nakamura
IBM
27 Papers
129 Citations
Yutaka Nakamura is an academic researcher from IBM. The author has contributed to research in topics: Sense amplifier & Logic gate. The author has an hindex of 11, co-authored 27 publications.
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Papers
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla,John V. Arthur,Rodrigo Alvarez-Icaza,Andrew S. Cassidy,Jun Sawada,Filipp Akopyan,Bryan L. Jackson,Nabil Imam,Chen Guo,Yutaka Nakamura,Bernard Brezzo,Ivan Vo,Steven K. Esser,Rathinakumar Appuswamy,Brian Taba,Arnon Amir,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +19 more
TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
4.2K
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan,Jun Sawada,Andrew S. Cassidy,Rodrigo Alvarez-Icaza,John V. Arthur,Paul A. Merolla,Nabil Imam,Yutaka Nakamura,Pallab Datta,Gi-Joon Nam,Brian Taba,Michael P. Beakes,Bernard Brezzo,Jente B. Kuang,Rajit Manohar,William P. Risk,Bryan L. Jackson,Dharmendra S. Modha +17 more
TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
1.5K
A 14 nm Embedded STT-MRAM CMOS Technology
Daniel C. Edelstein,Michael Rizzolo,Devika Sil,Ashim Dutta,J. DeBrosse,M.R. Wordeman,Abraham Arceo,Chu Isabel Cristina,James J. Demarest,E. R. J. Edwards,E. R. Evarts,J. Fullam,A. Gasasira,Guohan Hu,M. Iwatake,R. Johnson,V. Katragadda,T. Levin,James Chingwei Li,Yaocheng Liu,C. Long,Thomas M. Maffitt,S. McDermott,Sanjay Mehta,Virat Mehta,Dominik Metzler,J. Morillo,Yutaka Nakamura,Son Nguyen,P. Nieves,V. Pai,Raghuveer R. Patlolla,R. Pujari,Richard G. Southwick,Theodorus E. Standaert,O. van der Straten,Heng Wu,C.-C. Yang,D. Houssameddine,J. M. Slaughter,Daniel C. Worledge +40 more
- 12 Dec 2020
TL;DR: In this paper, the authors presented the first embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node, which supports the highest eMRAM density (0.0273 um2 cell size), optimal magnetic tunnel junction (MTJ) placement between M1-M2 for performance and density, and the lowest-cost integration scheme, with only 3 added mask levels (2 critical + 1 noncritical) and a single added electrode module.
52
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
Gary S. Ditlow,Robert K. Montoye,Salvatore N. Storino,Sherman M. Dance,Sebastian Ehrenreich,Bruce M. Fleischer,Thomas W. Fox,Kyle M. Holmes,Junichi Mihara,Yutaka Nakamura,Shohji Onishi,Robert Shearer,Dieter Wendel,Leland Chang +13 more
- 07 Apr 2011
TL;DR: This paper describes detailed implementation and measured hardware characteristics of this array and demonstrates a fast error correction scheme, and the techniques used balance high efficiency and low latency.
39
A full bit prefetch architecture for synchronous DRAM's
TL;DR: A high performance data path circuit design for Synchronous DRAM's (SDRAM's) is described, which enables low active power data burst operations because high frequency clock driven circuits are limited to the data path only.
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