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A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA

This paper demonstrates an architecture for accelerating the polynomial multiplication using number theoretic transform (NTT). Kyber is one of the finalists in the third round of the NIST post-quantum cryptography standardization process. Simultaneously, the performance of NTT execution is its main challenge, requiring large memory and complex memory access pattern. In this paper, an efficient NTT architecture is presented to improve the respective computation time. We propose several optimization strategies for efficiency improvement targeting different performance requirements for various applications. Our NTT architecture, including four butterfly cores, occupies only 798 LUTs and 715 FFs on a small Artix-7 FPGA, showing more than 44% improvement compared to the best previous work. We also implement a coprocessor architecture for Kyber KEM benefiting from our high-speed NTT core to accomplish three phases of the key exchange in 9, 12, and $\mathbf{19}\mu \mathbf{s}$ , respectively, operating at 200 MHz.

High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography

Large scale quantum computers will break classical public-key cryptography protocols by quantum algorithms such as Shor’s algorithm. Hence, designing quantum-safe cryptosystems to replace current classical algorithms is crucial. Luckily there are some post-quantum candidates that are assumed to be resistant against future attacks from quantum computers, and NIST is considering standardizing them. Among these candidates, lattice-based cryptography sounds more interesting than others due to the performance results as well as confidence in the security. There are few works in the literature evaluating the performance of lattice-based cryptography in hardware. In this paper, we focus on Cryptographic Suite for Algebraic Lattices (CRYSTALS) key exchange mechanisms known as Kyber and provide an instruction-set hardware architecture and implement on Xilinx Artix-7 FPGA for performance evaluation and testing. Our proposed architecture provides an efficient and high-performance set of components to perform polynomial sampling, number-theoretic transform (NTT), and point-wise multiplication to speed up lattice-based post-quantum cryptography (PQC). This architecture implemented on ASIC outperforms state-of-the-art implementations.

Instruction-Set Accelerated Implementation of CRYSTALS-Kyber

Efficient lattice-based cryptosystems operate with polynomial rings with the Number Theoretic Transform (NTT) to reduce the computational complexity of polynomial multiplication. NTT has therefore become a major arithmetic component (thus computational bottleneck) in various cryptographic constructions like hash functions, key-encapsulation mechanisms, digital signatures, and homomorphic encryption. Although there exist several hardware designs in prior work for NTT, they all are isolated design instances fixed for specific NTT parameters or parallelization level. This paper provides an extensive study of flexible design methods for NTT implementation. To that end, we evaluate three cases: (1) parametric hardware design, (2) high-level synthesis (HLS) design approach, (3) and design for software implementation compiled on soft-core processors, where all are targeted on reconfigurable hardware devices. We evaluate the designs that implement multiple NTT parameters and/or processing elements, demonstrate the design details for each case, and provide a fair comparison with each other and prior work. On a Xilinx Virtex-7 FPGA, compared to HLS and processor-based methods, the results show that the parametric hardware design is on average 4.4x and 73.9x smaller and 22.5x and 19.3x faster, respectively. Surprisingly, HLS tools can yield less efficient solutions than processor-based approaches in some cases.

An Extensive Study of Flexible Design Methods for the Number Theoretic Transform

Efficient lattice-based cryptosystems operate with polynomial rings with the Number Theoretic Transform (NTT) to reduce the computational complexity of polynomial multiplication. NTT has therefore become a major arithmetic component (thus computational bottleneck) in various cryptographic constructions like hash functions, key-encapsulation mechanisms, digital signatures, and homomorphic encryption. Although there exist several hardware designs in prior work for NTT, they all are isolated design instances fixed for specific NTT parameters or parallelization level. This article provides an extensive study of flexible design methods for NTT implementation. To that end, we evaluate three cases: (1) parametric hardware design, (2) high-level synthesis (HLS) design approach, and (3) design for software implementation compiled on soft-core processors, where all are targeted on reconfigurable hardware devices. We evaluate the designs that implement multiple NTT parameters and/or processing elements, demonstrate the design details for each case, and provide a fair comparison with each other and prior work. On a Xilinx Virtex-7 FPGA, compared to HLS and processor-based methods, the results show that the parametric hardware design is on average <inline-formula><tex-math notation="LaTeX">$4.4\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$73.9\times$</tex-math></inline-formula> smaller and <inline-formula><tex-math notation="LaTeX">$22.5\times$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$19.3\times$</tex-math></inline-formula> faster, respectively. Surprisingly, HLS tools can yield less efficient solutions than processor-based approaches in some cases. 

Lattice based cryptography plays an important role in the construction of post-quantum cryptography, including key exchange, public key encryption as well as digital signature schemes. Dating back to 2016, a new key exchange scheme called NewHope was proposed by Alkim, Ducas, Poppelmann, and Schwabe that based security on the quantum hardness of Ring Learning with Errors (RLWE) problem, and was later submitted to the NIST public competition of standard post-quantum cryptography. The new scheme is attractive as it is designed to achieve high performance. In this work, we concentrate on its performance on hardware platforms and propose an efficient implementation of NewHope on Xilinx Artix-7 7020 FPGA platform that consumes 3158 slices, 10285 LUTs, 6623 registers in the server side, and 3042 slices, 10345 LUTs, 6704 registers in the client side, achieving a 45% reduction in LUT, 30% reduction in FF while the total time utilization also decreases by 16% compared with the up to date and directly related work. Specifically, we can accomplish three phases of the key exchange in 39.8/61.7/ $21.4~\mu \text{s}$ respectively, operating in 153/152 MHz in server/client side.

An Efficient Implementation of the NewHope Key Exchange on FPGAs

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An Efficient Implementation of the NewHope Key Exchange on FPGAs