A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitallycontrolled oscillator (DCa) including a sigma- delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word.

A digital phase-locked loop clock system

A loop filter for receiving an input signal indicative of a phase-difference between a reference signal and a signal output by a signal generator and forming a control signal for controlling the signal generator in dependence thereon, the loop filter comprising a plurality of filter components that determine the frequency response of the filter, said filter components being arranged so that a first set of said components determines one or more zeros of the filter's frequency response and a second set of said components determines one or more poles of the filter's frequency response, each of said first and second sets of filter components being independent of the other such that the zero(s) and pole(s) of the filter's frequency response may be selected independently

Phase-Locked Loop

Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator. The method further includes testing the selected mathematical model using a sampled version of the correction signal such that the selected mathematical model can be used without the need for a testing duration that is in addition to a period of time used for the training.

System and method for built in self test for timing module holdover

Systems and methodologies are described that facilitate supporting VPLMN-autonomous CSG roaming in a wireless communication environment. A UE can access a CSG list server associated with a VPLMN. A trust relation can be established between the UE and the CSG list server, for example. Moreover, the CSG list server can update a VPLMN allowed CSG list associated with the VPLMN stored by the UE. Hence, the UE can receive the VPLMN allowed CSG list from the CSG list server associated with the VPLMN. Further, the UE can store the VPLMN allowed CSG list as part of an allowed CSG list. The VPLMN allowed CSG list can include one or more entries associated with the VPLMN. Moreover, the allowed CSG list can be under control of at least one operator and the UE.

Management of allowed csg list and vplmn-autonomous csg roaming

A method is disclosed for providing syntonisation, synchronization, position or some combination to a wireless base station, micro-cell, pico-cell, femto-cell or access point, by providing holdover backup in a GPS clock module via at least one interface between the GPS clock module and an external time or frequency reference Switching between synchronization modes is designed to occur on the control side of the oscillator portion of the module rather than at the output of two oscillators A corresponding GPS clock module apparatus is disclosed for providing holdover backup via at least one interface between the GPS clock module and external time or frequency references

Gps-based multi-mode synchronization and clocking femto-cells, pico-cells and macro base stations

A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value.

Method for binary clock and data recovery for fast acquisition and small tracking error

A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Digitally compensated highly stable holdover clock generation techniques using adaptive filtering

A method and apparatus for auto-frequency calibration for multi-band VCO have been disclosed where a VCO is first adjusted to a major frequency band and then adjusted to a sub-band within the major frequency band.

Method and apparatus for auto-frequency calibration for multi-band VCO

A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.

Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design

A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.

High speed chip screening method using delay locked loop

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