Yixin Xu
19 Papers
Yixin Xu is an academic researcher. The author has contributed to research in topics: Computer science & Scalability. The author has an hindex of 2, co-authored 11 publications.
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Papers
Quasi-Nondestructive Read Out of Ferroelectric Capacitor Polarization by Exploiting a 2TnC Cell to Relax the Endurance Requirement
Yi Xiao,Shan Deng,Zijian Zhao,Zubair Faris,Yixin Xu,Tzu-Jung Huang,Vijaykrishnan Narayanan,Kai Ni +7 more
TL;DR: In this article , the authors exploit a 2TnC ferroelectric random access memory (FeRAM) cell design to realize the quasi-nondestructive readout (QNRO), which can relax the endurance requirement of the FeRAM thin film and exploits the benefits of both FeRAM and FeFET.
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On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond
Yi Xiao,Yixin Xu,Zhouhang Jiang,Shan Deng,Zijian Zhao,Antik Mallick,Limeng Sun,Rajiv V. Joshi,Xueqing Li,Nikhil Shukla,Vijaykrishnan Narayanan,Kai Ni +11 more
- 03 Dec 2022
TL;DR: In this paper , a comprehensive model which reflects two FeFET write mechanisms was proposed, one to ground Source (S), Drain (D) & Body (B) nodes and use Gate (G) to write, and the other to float S/D and use G & B to write.
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ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories
Taixin Li,Bo Yuan Sun,Hongtao Zhong,Yixin Xu,Vijaykrishnan Narayanan,Liang Shi,Tian Wang,Yao Yu,Thomas Kämpfe,Kai Ni,Huazhong Yang,Xueqing Li +11 more
TL;DR: ProtFe as mentioned in this paper leverages the unique features of Ferroelectric field effect transistors (FeFETs) and proposes the protection methods for FeFET-based memories, including the pipelined multi-step write strategy (PiMWrite) and the split array design (SpA).
WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators
Zhonghao Chen,Yiming Chen,Yixin Xu,Tian Wang,Yao Yu,Vijaykrishnan Narayanan,Sumitha George,Huazhong Yang,Xueqing Li +8 more
- 11 Jun 2023
TL;DR: WeightLock as discussed by the authors proposes a mixed-grained hardware-software co-design approach based on local decrypting units (LDUs), which shows >20% higher key leakage tolerance and >17x longer retraining latency protection.
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A Module-Level Configuration Methodology for Programmable Camouflaged Logic
Jianfeng Wang,Zhonghao Chen,Jiahao Zhang,Yixin Xu,Tongguang Yu,Enze Ye,Ziheng Zheng,Huazhong Yang,Sumitha George,Yongpan Liu,N. Vijaykrishnan,Xueqing Li +11 more
TL;DR: This work proposes a novel module-level configuration methodology for programmable camouflaged logic that can be implemented without additional hardware ports and with negligible resources, and proves theoretically that the configuration of the programmable camouflaged logic cells can be achieved through the inputs and netlist of the original module.
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