This paper introduces a low-energy variation-tolerant asynchronous ternary content-addressable memory (TCAM) for Network Intrusion Detection Systems (NIDS). The proposed special-purpose TCAM can detect packet payloads as "virus free" by inspecting only a few bytes. Hence, it adaptively cancels unnecessary searches, leading to greatly reduction in the search delay time and energy dissipation. For timing robustness with low area overhead, a word circuit that stores a virus pattern is designed based on both a quasi-delay insensitive (QDI) and a bundled-data techniques. The QDI word circuit is realized by combining complementary word circuits for only a small portion of the TCAM that is sensitive to delay variations. For performance evaluation, a probability of the virus detection is calculated using a set of real packet traces from MIT DARPA. A 2048 × 128-byte asynchronous TCAM is designed using TSMC 65nm CMOS technology. The energy dissipation is 93.1% lower and the cycle time is 52.4% lower than those of a deep-pipelined synchronous TCAM with a comparable area. It is also demonstrated that the proposed TCAM tolerates up to 47% variations (3s) of threshold voltages.

A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems

Many telecommunications devices such as network switches contain content addressable memories (CAMs) for uses such as routing tables. CAMs, a class of associative memories, contain considerable logic for various forms of content matching and can be considered a class of reconfigurable logic engines. This paper demonstrates how a commercial ternary CAM and traditional RAM can be used with minimal additional logic to implement over 90% of the Snort 2.0 intrusion detection system (IDS) at line speeds of or exceeding 1 Gbs. In addition to simple matching techniques, sophisticated matching operations required by Snort can be implemented by levering an iterative approach that leverages a post processing action RAM. Additionally, a novel range encoding algorithm allows range matching required in the CAM for which other encodings either exceed the width provided by a CAM entry, or require excessive number of CAM entries to be scalable. The system was implemented for verification and performance evaluation in cycle accurate simulation using SystemC.

A CAM-based intrusion detection system for single-packet attack detection

UCL (Uniform Content Locator) which can be used in information management and semantic comprehension has attracted more and more attentions from researchers. In this paper, a hardware system of UCL filtering based on FPGA is proposed. In addition a new type of CAM (Content Addressable Memory) and a hardware platform are designed. In experimental environment, the BIP (Broadcasting Internet Protocol) packets formed by indexing UCL in source side are delivered to user terminals, and the filtering system realizes UCL resolving with FPGA in Ethernet. The results show that the system filtering rate is up to 10Mbit/S and maximum frequency reaches 238MHz.

Design of UCL hardware filtering system based on FPGA

The Internet is the universal network infrastructure that surrounds the Earth with thousands of devices and connections that make up it. The communication of various technologies from data centers to personal smartphones is provided through this infrastructure. While end devices are renewed as technology and product in short periods, network devices such as switches and routers, where communication is provided, can work for many years and work with out-of-date software and protocols. Therefore, it is clear how important the weaknesses are. Internet communication protocols are designed with security concerns in mind instead of communication speed and bandwidth. Even though researchers work intensively on wireless networks, the security of the infrastructure that connects wireless networks is ignored. In this study, we examined the attacks on OSI layer 2 and layer 3 layers made to the devices that constitute the backbone of the Internet infrastructure. Although several security measures and updates have been published for some of these attacks, the vulnerabilities that may occur in outdated devices are revealed.

A Survey on Backbone Attack

Network-based Intrusion Prevention System (NIPS) monitors network traffic for suspicious activity and has ability to subvert or stop an attack targeted at any system or device in network. With an advent of 10G/40G Ethernet standards, current generation NIPS components may not cope up with these network speeds. In this work, FPGA-based architecture for key functionalities of NIPS have been designed and evaluated. Here, network traffic is processed from Layer 1(physical) till Layer 4(transport) using FPGA logic resources. The concurrent behavior of hardware is exploited for processing packets at 10 Gbps received from Ethernet interface. A Receive Decode Module (RXDM) is proposed to extract essential data for intrusion analysis. This information is then analyzed by Packet Processing Engine (PPE) which is heart of this architecture and decision is taken as per defined policies to pass or drop ongoing packet.

Hardware implementation of key functionalities of NIPS for high speed network

Content addressable memory (CAM) is a parallel search engine chip that has been proven to accelerate network appliance functions that are search-intensive by nature, such as routing table lookups. CAMs enable searching for a match of a single input with hundreds of thousands of entries in parallel in a single clock cycle. However, CAMs are inefficient in matching a numeric range with existing encoding methods. Two-hot, binary and Gray encodings exhibit a depth scalability problem where the CAM depth required increases with the maximum number M in the range. One-hot and Johnson encodings exhibit poor CAM width scalability O(M). We present a unique hybrid encoding scheme mixing the features of two-hot and Johnson codes to solve both scalability problems. For an arbitrary range, it uses only three CAM entries in depth regardless of M, and has a width scaling of O(/spl radic/M ). Therefore, this hybrid encoding scheme can be efficiently applied to CAM-based range matching with arbitrary ranges, while maintaining single cycle searching.

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory

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A CAM-based intrusion detection system for single-packet attack detection

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory

A Gigabit Embedded Protocol Analyzer Pre-Processor