Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence (AI). In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor has developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, self-rectifying memristor (SRM) has been proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (∼aJ) and scalability (> 102 Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed. This article is protected by copyright. All rights reserved.

Self-Rectifying Memristors for Three-Dimensional in-Memory Computing.

With the rapid development of 5G technology, its high bandwidth, high reliability, low delay, and large connection characteristics have opened up a broader application field of IoT. Moreover, AIoT (Artificial Intelligence Internet of Things) has become the new development direction of IoT. Through deep learning of real-time data provided by the Internet of Things, AI can judge user habits more accurately, make devices behave in line with user expectations, and become more intelligent, thus improving product user experience. However, in the process, there is a lot of data interaction between the edge and the cloud. Given that the shared data contain a large amount of private information, preserving information security on the shared data is an important issue that cannot be neglected. In this paper, we combine deep learning with homomorphic encryption algorithm and design a deep learning network model based on secure multiparty computing (MPC). In the whole process, we realize that the cloud only owns the encryption samples of users, and users do not own any parameters or structural information related to the model. In the experimental part, we input the encrypted Mnist and Cifar-10 datasets into the model for testing, and the results show that the classification accuracy rate of the encrypted Mnist can reach 99.21%, which is very close to the result under plaintext. The classification accuracy rate of encrypted Cifar-10 can reach 91.35%, slightly lower than the test result in plaintext and better than the existing deep learning network model that can realize data privacy protection.

/pdf/deep-learning-data-privacy-protection-based-on-homomorphic-3d11g8gtyu.pdf

Deep Learning Data Privacy Protection Based on Homomorphic Encryption in AIoT

A novel Resistive random access memory (ReRAM)-based Compute-in-memory (CIM) macro is proposed to overcome the limited accuracy and throughput of a conventional ReRAM-based CIM macro that results from to the low R-Ratio and large variation of ReRAM. The proposed structure consists of 1T2R1C bit-cells and 4-kb ReRAM-based nvCIM architecture with ternary weight and ternary input. Ternary multiplication is implemented with voltage division between paired ReRAM devices within a bit-cell to make the output voltage variation tolerant and less sensitive to low R-ratios. An accumulation operation is realized with capacitive coupling so that linearity can be guaranteed for a large number of operands, allowing accurate and fast multiply-and-accumulate (MAC) operations. For comprehensive validation of the proposed CIM macro, the Verilog-A models for ReRAM devices with an adjustable R-ratio and adjustable variations are adopted to perform simulation on various R-ratio and variation conditions. With the peripheral circuits designed in 180-nm CMOS technology, the proposed CIM macro is confirmed to have high variation tolerance, high throughput, and less sensitivity to a low R-ratio, resulting in a high ternary DNN accuracy of 99.07% (0.01% drop) for the MNIST and 83.79% (0.38% drop) for the CIFAR-10 data sets with an R-ratio as low as 38 and 20%/40% low/high resistance variation.

Variation-Tolerant and Low R-Ratio Compute-in-Memory ReRAM Macro With Capacitive Ternary MAC Operation

This work presents a fully-digital 64 Kb non-volatile ReRAM based compute-in-memory (CIM) macro for the modern artificial intelligence (AI) edge devices, using 65 nm technology. This digital CIM architecture effectively removes the analog-design issues, related to process variations, noise susceptibility, and data-conversion overhead. Hence, it offers no accuracy loss and high energy-efficiency for the computation. To incorporate the digital computation, a novel NAND logic based 3.25T1R bitcell is proposed. The digital behaviour of this cell makes it superior to the conventional 1T1R based analog bitcell. Also, with the inherent non-volatility of ReRAM, the proposed cell can be a good substitute for SRAM-based CIM architectures with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.62\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.96\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.96\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.12\times $ </tex-math></inline-formula> lower area than the XNOR-based 12T, Twin-8T, 8T, and 6T SRAM cell respectively. Moreover, the proposed CIM architecture allows full reconfigurabiliy from 1 to 16b precision for both input and weight. It also allows activating any number of parallel inputs, ranging from 1 to 128. According to simulation results, the proposed macro successfully operates up to 166.6 MHz for 1/8/15b input/weight/output precision and achieves 27.28 TOPS/W without any accuracy loss. Removing sense amplifiers for the ReRAM mode of the proposed work claims additional area and power savings. 

A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications

The convergence of artificial intelligence (AI) is one of the critical technologies in the recent fourth industrial revolution. The AIoT (Artificial Intelligence Internet of Things) is expected to be a solution that aids rapid and secure data processing. While the success of AIoT demanded low-power neural network processors, most of the recent research has been focused on accelerator designs only for inference. The growing interest in self-supervised and semi-supervised learning now calls for processors offloading the training process in addition to the inference process. Incorporating training with high accuracy goals requires the use of floating-point operators. The higher precision floating-point arithmetic architectures in neural networks tend to consume a large area and energy. Consequently, an energy-efficient/compact accelerator is required. The proposed architecture incorporates training in 32 bits, 24 bits, 16 bits, and mixed precisions to find the optimal floating-point format for low power and smaller-sized edge device. The proposed accelerator engines have been verified on FPGA for both inference and training of the MNIST image dataset. The combination of 24-bit custom FP format with 16-bit Brain FP has achieved an accuracy of more than 93%. ASIC implementation of this optimized mixed-precision accelerator using TSMC 65nm reveals an active area of 1.036 × 1.036 mm2 and energy consumption of 4.445 µJ per training of one image. Compared with 32-bit architecture, the size and the energy are reduced by 4.7 and 3.91 times, respectively. Therefore, the CNN structure using floating-point numbers with an optimized data path will significantly contribute to developing the AIoT field that requires a small area, low energy, and high accuracy.

/pdf/optimal-architecture-of-floating-point-arithmetic-for-neural-2rrqqg8h.pdf

Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors

To reduce the energy-consuming and time latency incurred by Von Neumann architecture, this brief developed a complete computing-in-memory (CIM) convolutional macro based on ReRAM array for the convolutional layers of a LeNet-like convolutional neural network (CNN). We binarized the input layer and the first convolutional layer to get higher accuracy. The proposed ReRAM-CIM convolutional macro is suitable as an IP core for any binarized neural networks’ convolutional layers. This brief customized a bit-cell consisting of 2T2R ReRAM cells, regarded ${9 \times 8}$ bit-cells as one unit to achieve high hardware compute accuracy, great read/compute speed, and low power consuming. The ReRAM-CIM convolutional macro achieved 50 ns product-sum computing time for one complete convolutional operation in a convolutional layer in the customized CNN, with an accuracy of 96.96% on MNIST database and a peak energy efficiency of 58.82 TOPS/W.

A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications

Hardware encryption primitives such as physical unclonable functions (PUFs) are used in power and cost limited Internet of Things (IoT) and computing on edge devices. Resistive random access memory (RRAM) PUF is proposed as an alternative to CMOS one. But due to the existence of transistors as selectors, it still shares the drawbacks of CMOS PUF. In this work, a homogeneous and efficient PUF was constructed out of 3-D selector-free RRAM. It is immune to ray attack and fault injection and features low power, thanks to the absence of transistors and high-resistance states of the RRAM cells. The inter- and intra-Hamming distances (HDs) are measured to be 50.02% and 0%, respectively, which well validates its uniqueness and reliability. Experimental results show that the proposed PUF can be operated with a low energy consumption of 144 fJ/bit, and a compact bit-cell area of 16 $\text{F}^{{2}}$ /bit. The digital values in the cells can maintain for over 100 h at 85 °C, which is equivalent to 24 years under 40 °C. Besides, given that the selector-free structure renders the PUF instance homogeneous, the PUF instance has enhanced security performance against radiation.

A Homogeneous, Reconfigurable, and Efficient Implementation of PUF in 3-D Selector-Free RRAM

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A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications

A Homogeneous, Reconfigurable, and Efficient Implementation of PUF in 3-D Selector-Free RRAM