Coarse Grained Reconfigurable Arrays (CGRA) are more area and energyefficient compared to FPGAs, if we consider applications that aredominated by arithmetical operations. Enabling the user to employCGRAs requires tools to create suitable CGRA instances and to programthem on a high abstraction level. In this contribution we brieflyexplain a CGRA archticture generator and we focus on the schedulerthat programs the generated CGRAs. This scheduler is able to work oninhomogeneous (concerning the operations in the processing elements) and irregular (concerning the connections between processing elements) compositions. Additionally, the scheduler is able to map complex controlflow onto the CGRA, which means nested loops, even containing controlflow in the loop body. This significantly increases the mappability ofapplication kernels.

Scheduler for Inhomogeneous and Irregular CGRAs with Support for Complex Control Flow

Coarse-Grained Reconfigurable Architectures (CGRAs) emerged about 30 years ago. The very first CGRAs were programmed manually. Fortunately, some compilation approaches appeared rapidly to automate the mapping process. Numerous surveys on these architectures exist. Other surveys also gather the tools and methods, but none of them focuses on the mapping process only. This paper focuses solely on automated methods and techniques for mapping applications on CGRA and covers the last two decades of research. This paper aims at providing the terminology, the problem formulation, and a classification of existing methods. The paper ends with research challenges and trends for the future.

Twenty Years of Automated Methods for Mapping Applications on CGRA

Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors

Embedded devices are playing a vital role in today's day-to-day life. The devices like mobile, washing machine, microwave may be considered as a result of advancement in embedded systems. There are design limitations on processor area and energy consumption of embedded processors. Energy consumption will be considered as one of the important parameters in performance enhancement of embedded processor. The energy drawn by on-chip cache has an identifiable share in the total energy supplied to the processor. This paper presents a survey of different techniques to improve the energy consumption. The parameters considered in survey are dynamic energy, area, throughput, performance, lifetime, harmonic mean instruction per cycle, miss rate and latency. This survey has identified the need of an energy efficient technique with respect to the writes.

A Survey on Performance of On-Chip Cache for Multi-core Architectures

Les architectures reconfigurables a gros grains offrent un compromis flexibilite-performance interessant a travers les nombreuses unites de calculs elementaires qu'elles proposent Cependant, projeter automatiquement une application sur une architecture reconfigurable a gros grain est un processus complexe qui necessite d'explorer un vaste espace de solutions 
Cet article propose d'etudier l'apport d'aleas dans le processus de projection L'introduction d'aleas est effectue en particulier dans les etapes d'ordonnancement et d'assignation Differentes strategies permettant de garantir un nombre minimum et maximum de solutions sont presentees Les resultats montrent que notre methode, couplee a une approche de transformation du graphe d'application, explore mieux l'espace de solutions et permet de trouver la latence la plus courte

https://hal.archives-ouvertes.fr/hal-01347737/document

Introduction d'aléas dans le processus de projection d'applications sur CGRA

Stacked-DRAM used as the last-level caches(LLC) in multi-core systems delivers performance enhancement due to its capacity benefit. While the performance of LLC depends heavily upon its block replacement policy, conventional replacement policy needs redesigning to exploit the best of DRAM cache while avoiding its drawbacks. Existing DRAM cache insertion policy blindly forwards victim lines to the off-chip memory, regardless of the potential for increased hits by placing a fraction of them in the DRAM cache; nevertheless, a na¨ive design that steers all dirty victims to the DRAM cache introduces excessive writeback traffic which aggravates capacity misses and DRAM interference. To leverage insertions in terms of writeback or fill requests, we propose a cooperative writeback and insertion policy that adapts to the distinct access patterns of heterogeneous applications based on runtime misses and writeback efficiency, thereby increasing HMIPC (harmonic instruction per cycle) throughput by 22.2%, 13.7% and 14.5% compared to LRU and two static writeback policies.

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache

Coarse-Grained Reconfigurable Architectures (CGRAs) are the promising architectures with high performance, high power- efficiency and attractions of flexibility. The computation-intensive portions of application, i.e. loops, are often implemented on CGRAs for acceleration. The loop pipelining techniques are usually used to exploit the parallelism of loops. However, for nested loops, the existing loop pipelining methods often result in poor hardware utilization and low execution performance. To tackle this problem, this paper makes two contributions: 1) a pipelining-beneficial affine transformation method which can optimize the initiation interval (II) of nested loop and enable multiple loop pipelines merging; 2) a multi-pipeline merging method which can improve hardware utilization further. The experimental results show that our approach can improve the performance of nested loop by up to 56% on average, as compared to the state-of-the-art techniques.

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs

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Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs