Recently, multilevel inverters (MLIs) have gained lots of interest in industry and academia, as they are changing into a viable technology for numerous applications, such as renewable power conversion system and drives. For these high power and high/medium voltage applications, MLIs are widely used as one of the advanced power converter topologies. To produce high-quality output without the need for a large number of switches, development of reduced switch MLI (RS MLI) topologies has been a major focus of current research. Therefore, this review paper focuses on a number of recently developed MLIs used in various applications. To assist with advanced current research in this field and in the selection of suitable inverter for various applications, significant understanding on these topologies is clearly summarized based on the three categories, i.e., symmetrical, asymmetrical, and modified topologies. This review paper also includes a comparison based on important performance parameters, detailed technical challenges, current focus, and future development trends. By a suitable combination of switches, the MLI produces a staircase output with low harmonic distortion. For a better understanding of the working principle, a single-phase RS MLI topology is experimentally illustrated for different level generation using both fundamental and high switching frequency techniques which will help the readers to gain the utmost knowledge for advance research.

/pdf/recently-developed-reduced-switch-multilevel-inverter-for-4lxrfejht6.pdf

Recently Developed Reduced Switch Multilevel Inverter for Renewable Energy Integration and Drives Application: Topologies, Comprehensive Analysis and Comparative Evaluation

The Neutral Point Clamped (NPC) Multi-Level Inverters (MLI) have been ruling the power electronics industries for the past two decades. The Multi-Carrier Pulse Width Modulation (MCPWM) is common PWM techniques which are widely used in NPC-MLI applications. However, MCPWM is not having a good impact on the balancing of DC-link voltages, Common Mode Voltage (CMV) and limiting the Total Harmonics Distortion (THD). The Selective Harmonic Elimination (SHE) technique is introduced for reducing the THD, however all the switching angles should be maintained less than $\pi $ /2 to keep the eliminated harmonics at constant level which narrows down the modulation index range. Hence, in recent days Space Vector Modulation (SVM) technique is widely used in NPC-MLI, which gives better DC-link voltage balancing, self-neutral point balancing, near-zero CMV reduction, better-quality harmonics profile and switching loss minimization. Hence, it is a preferred solution for the majority of electrical conversion applications such as electric traction, high power industrial drives, renewable power generation, and grid-connected inverters, etc. The paper gives a comprehensive review of the SVM for NPC-MLI. First, this paper deliberates the state of art for two-level SVM and extends it to three-level (3L) SVM. Also compares the 3L SVM performance with other MCPWM techniques. Followed by the various modified MLI SVM techniques in terms of their implementations, DC-link capacitor balancing, and reduction of CMV. Further, the review of MLI SVM is widened to open-end winding Inverters and multiphase MLIs. The final part of this paper discussed the future trends and research directions on MLI SVM techniques and its applications.

/pdf/a-comprehensive-review-on-space-vector-modulation-techniques-4knkky1lpu.pdf

A Comprehensive Review on Space Vector Modulation Techniques for Neutral Point Clamped Multi-Level Inverters

Neutral-point voltage imbalance is one of the main problems of five-level neutral-point clamped inverters that impedes their industrial application. In order to solve this problem, a closed-loop neutral-point voltage balancing method based on carrier-overlapped pulsewidth modulation (COPWM) is proposed in this article. The four dc-link capacitor voltages are balanced by three steps: voltage balancing between the two outer capacitors, voltage balancing between the two inner capacitors, and voltage balancing between the two inner and the two outer capacitors. The relationship between the neutral-point currents and the reference voltage is studied, and the top and the bottom dc-link capacitor voltages are balanced by zero-sequence voltage injection. The two inner capacitor voltages are balanced by adjusting the width of switching signals. Simulation and experimental results are presented to confirm the validity of this method.

Neutral-Point Voltage Balancing Method for Five-Level NPC Inverters Based on Carrier-Overlapped PWM

In this paper, a new 5-level inverter is developed by inserting a switched-capacitor (SC) unit into the traditional 3-level neutral-point-clamped (NPC) inverter phase-leg. The SC unit consists of two capacitors and one bidirectional switch, all of which withstand a quarter of the dc input voltage. Whilst increasing the output levels, the performance is also improved in terms of power loss, common-mode voltage, switching stress dv/dt and output filter. Compared to other 5-level inverters like the conventional NPC and active NPC 5-level topologies, the new solution not only reduces the number of components and simplifies the design, but also has the advantage of self-balanced capacitor voltages. The analysis, simulation and experiment indicate that the proposed inverter is suitable for a wide range of applications like renewable source grid-connected interfaces and motor drivers. Simulation and experimental results of grid-connected operation verify that the new inverter is capable of providing both active and reactive power to the grid. Its excellent performance is also experimentally evaluated by a 1.2 kW prototype and the measured efficiency is above 97% for a wide range of load.

Neutral-Point-Clamped Five-Level Inverter with Self-Balanced Switched-Capacitor

The powertrain voltages in battery electric vehicles (BEVs) have witnessed an upward trend due to advantages such as reduced runtime losses and extremely high DC fast charging power levels; aiding in reduced range anxiety and lower battery charging duration. This trend requires original equipment manufacturers (OEMs) to re-assess the design of electronic sub-assemblies (ESAs). Due to newly released DC fast charging standards, there are implications on the on-board charger (OBC), which is one of the ESAs in a BEV. This paper performs a comprehensive review of identifying system-level and use-case related challenges in transitioning on-board chargers to higher voltages compared to state-of-the-art, while considering the impact of newly introduced DC fast charging standards like Megawatt Charging Systems (MCS) and ChaoJi/ CHAdeMO 3.0. The existing research in academia and proof-of-concept designs compatible for high-voltage on-board charging sub-systems, such as the power factor correction (PFC) and isolated DC-DC conversion stages is consolidated. Due to the demand for integration driven by cost-optimization targets, single-stage, traction-integrated, and auxiliary power unit (APU) integrated on-board chargers are discussed. Finally, the disparity between state-of-the-art technology and future requirements is defined to establish challenges and the direction of future research areas. 

/pdf/on-board-chargers-for-high-voltage-electric-vehicle-16dk787l.pdf

On-Board Chargers for High-Voltage Electric Vehicle Powertrains: Future Trends and Challenges

Compared with full-SiC mosfet s converters, the hybrid utilization of Si/SiC converters is an alternative approach to achieve the tradeoff between performance and cost. A systematic method is proposed to generate 2-SiC and 4-SiC hybrid three-level active neutral-point-clamped (3L-ANPC) inverter topologies from two types of switching cells based on the arrangement of freewheeling paths. The 2-SiC hybrid 3L-APNC inverter and the 4-SiC hybrid 3L-ANPC inverter are analyzed in detail with switching states and modulation strategies given. The power losses are quantitatively compared between the 2-SiC hybrid 3L-ANPC inverter and the 4-SiC hybrid 3L-ANPC inverter. The junction operating temperatures of active switches in different hybrid 3L-ANPC inverters are also estimated. With the same specifications and switching device parameters, the maximum output power of the 4-SiC hybrid 3L-ANPC inverter with modulation strategy I is almost 1.47 times than that of the 2-SiC hybrid 3L-ANPC inverter. A universal prototype for the full-SiC scheme, the full-IGBT scheme, and different Si/SiC hybrid schemes is built to evaluate these topologies at conversion efficiency and thermal characteristics. Experimental results and analysis show that the full-SiC 3L-ANPC inverter has the highest efficiency, whereas the 2-SiC hybrid 3L-ANPC inverter has the best cost performance. Further, the 4-SiC hybrid 3L-ANPC inverter with modulation strategy I has better thermal balance characteristic than that of the 2-SiC hybrid 3L-ANPC inverter, which shows significant superiority in high power density applications.

Evaluation of Different Si/SiC Hybrid Three-Level Active NPC Inverters for High Power Density

Compared with full-silicon-carbide (SiC) mosfet converters, the hybrid utilization of Si/SiC converters is an alternative approach to achieve the tradeoff between performance and cost. In this article, a 2-SiC hybrid five-level active neutral-point-clamped (5L-ANPC) full-bridge inverter is proposed. The proposed inverter is constructed by combining a 2-SiC hybrid 3L-ANPC half-bridge inverter and a two-level half-bridge arm. The operation principle of the proposed inverter by using the conventional modulation scheme is analyzed in detail. Furthermore, a dedicated modulation scheme is proposed to lower the conduction losses. The calculated power losses of the 2-SiC hybrid 5L-ANPC full-bridge inverter with the conventional modulation scheme and the proposed modulation scheme are addressed and compared. The proposed modulation scheme exhibits higher efficiencies under high-power conditions. But the conventional modulation scheme shows efficiency superiority under low-power conditions. Therefore, a hybrid modulation scheme is also proposed to achieve an overall high efficiency performance. A 4-kW prototype is built to evaluate the proposed topology and its modulation scheme at conversion efficiency. Experimental results and analysis show that comparing to the conventional modulation scheme, the hybrid modulation scheme can reduce power loss without increasing the hardware cost.

A Si/SiC Hybrid Five-Level Active NPC Inverter With Improved Modulation Scheme

The utilization of wide bandgap devices such as silicon carbide (SiC) devices can significantly reduce the switching losses due to its fast switching speed. However, it cannot be widely used because of its high cost. Thus, "SiC+Si" hybrid topology is proposed. It only replaces a part of devices with SiC devices, thus the total cost is lower than that of the all-SiC-devices-based topology. Furthermore, the efficiency of the hybrid topology can be improved by applying suitable modulation strategies. Among all of the studies on hybrid applications, few attentions have been paid to reducing the conduction losses. This paper proposes an improved modulation strategy based on "SiC+Si" hybrid five-level active neutral point clamped inverter (FL-ANPC) topology, which can not only reduce the switching losses, but also reduce the conduction losses. In addition, as only two SiC MOSFETs are used, the cost is greatly reduced compared with the all-SiC-MOSFETs-based topology. Experimental results are presented to confirm the benefits of this proposed modulation strategy of FL-ANPC inverter.

An Improved Modulation Strategy for "SiC+Si" Hybrid Five-Level Active NPC Inverters

Neutral-point (NP) potential imbalance is a crucial issue in five-level NP clamped (5L-NPC) full-bridge inverters. The basic idea of the conventional closed-loop NP potential balancing control methods is to sample the voltages of split dc-link capacitors first and then regulate the modulation waveform according to different voltages of split dc-link capactiors. In this paper, an open-loop NP potential balancing control for 5L-NPC full-bridge grid-tied inverters (FB-GCIs) is proposed. A balancing factor $k$ is introduced into the modulation signals and regulated according to the calculation results of the modulation index. Therefore, although the voltages of split dc-link capacitors have not been sampled and controlled, the dc-link capacitor voltages can be balanced over a wide modulation index range. Both the switching states and the NP potential balancing region of the 5L-NPC FB-GCI are analyzed in detail. The design guidelines of the balancing factor $k$ are also presented. A 5L-NPC FB-GCI prototype is built for the experimental tests, and experimental results validate the feasibility and effectiveness of the proposed control method.

A Capacitor Voltage Balancing Control Method for Five-Level Full-Bridge Grid-Tied Inverters Without Split-Capacitor Voltage Sampling

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Papers

Evaluation of Different Si/SiC Hybrid Three-Level Active NPC Inverters for High Power Density

A Si/SiC Hybrid Five-Level Active NPC Inverter With Improved Modulation Scheme

An Improved Modulation Strategy for "SiC+Si" Hybrid Five-Level Active NPC Inverters

A Capacitor Voltage Balancing Control Method for Five-Level Full-Bridge Grid-Tied Inverters Without Split-Capacitor Voltage Sampling