10 Papers
56 Citations
Yasu Lu is an academic researcher from Hong Kong University of Science and Technology. The author has contributed to research in topics: Digital control & Ripple. The author has an hindex of 4, co-authored 6 publications.
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Papers
A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOS
Yasu Lu,Fan Yang,Feng Chen,Philip K. T. Mok +3 more
- 01 Feb 2018
TL;DR: This paper presents an on-chip DPDg with cooperative regulation based on an analog-assisted digital LDO (AADLDO), which inherits the merits of low output ripple and sub-LSB current supply ability from the analog control, and the advantage of low supply voltage operation and adaptive fast response from the digital control.
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A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS
TL;DR: This article proposes a digitally assisted analog low-dropout (DA-ALDO) regulator, a hybrid solution which realizes tight regulation, wide load current range, area-efficient power transistor utilization, and fast transient speed in the meantime.
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A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction
TL;DR: This paper introduces an on-chip distributed power delivery grid (DPDG) with cooperative regulation and IR-drop reduction based on analog-assisted digital LDOs (AADLDOs), which inherit the merits of low output ripple and sub-LSB current supply ability from the analog control.
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A Single-Controller-Four-Output Analog-Assisted Digital LDO with Adaptive-Time-Multiplexing Control in 65-nm CMOS
Yasu Lu,Feng Chen,Philip K. T. Mok +2 more
- 01 Sep 2019
TL;DR: A single-controller-four-output analog-assisted digital LDO which can regulate four output voltage domains by sharing only one digital controller with an adaptive-time-multiplexing control scheme is presented.
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A comparative analysis on binary and multiple-unary weighted power stage design for digital LDO
Fan Yang,Yasu Lu,Philip K. T. Mok +2 more
- 01 Oct 2016
TL;DR: An analytical study of designing power stage for the emerging digital LDO is presented, namely binary and multiple-unary weighted power stage sizing, which target at realizing a balanced speed and resolution of thedigital LDO.
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