Yao Yu
6 Papers
Yao Yu is an academic researcher. The author has contributed to research in topics: Computer science & Scalability. The author has an hindex of 1, co-authored 5 publications.
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Papers
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories
Taixin Li,Bo Yuan Sun,Hongtao Zhong,Yixin Xu,Vijaykrishnan Narayanan,Liang Shi,Tian Wang,Yao Yu,Thomas Kämpfe,Kai Ni,Huazhong Yang,Xueqing Li +11 more
TL;DR: ProtFe as mentioned in this paper leverages the unique features of Ferroelectric field effect transistors (FeFETs) and proposes the protection methods for FeFET-based memories, including the pipelined multi-step write strategy (PiMWrite) and the split array design (SpA).
WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators
Zhonghao Chen,Yiming Chen,Yixin Xu,Tian Wang,Yao Yu,Vijaykrishnan Narayanan,Sumitha George,Huazhong Yang,Xueqing Li +8 more
- 11 Jun 2023
TL;DR: WeightLock as discussed by the authors proposes a mixed-grained hardware-software co-design approach based on local decrypting units (LDUs), which shows >20% higher key leakage tolerance and >17x longer retraining latency protection.
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ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory
Hongtao Zhong,Zhonghao Chen,Wenqin Huangfu,Chen Wang,Yixin Xu,Tian Wang,Yao Yu,Yongpan Liu,N. Vijaykrishnan,Huazhong Yang,Xueqing Li +10 more
TL;DR: ASMCap as mentioned in this paper adopts charge-domain computing based on the capacitive multi-level content addressable memories (ML-CAMs), and outperforms the state-of-the-art EDAM with higher accuracy and energy efficiency.
GRAPHIC: Gather And Process Harmoniously In the Cache with High Parallelism and Flexibility
Yiming Chen,Mingyen Lee,Guohao Dai,Mufeng Zhou,Nagadastagiri Challapalle,Tian Wang,Yao Yu,Yongpan Liu,Yu Wang,Huazhong Yang,Vijaykrishnan Narayanan,Xueqing Li +11 more
Abstract: In-memory computing (IMC) has been proposed to overcome the von Neumann bottleneck in data-intensive applications. However, existing IMC solutions could not achieve both high parallelism and high flexibility, which limits their application in more general scenarios: As a highly parallel IMC design, the functionality of a MAC crossbar is limited to the matrix-vector multiplication; Another IMC method of logic-in-memory (LiM) is more flexible in supporting different logic functions, but has low parallelism. To improve the LiM parallelism, we are inspired by investigating how the single-instruction, multiple-data (SIMD) instruction set in conventional CPU could potentially help to expand the number of LiM operands in one cycle. The biggest challenge is the inefficiency in handling non-continuous data in parallel due to the SIMD limitation of (i) continuous address, (ii) limited cache bandwidth, and (iii) large full-resolution parallel computing overheads. This article presents GRAPHIC, the first reported in-memory SIMD architecture that solves the parallelism and irregular data access challenges in applying SIMD to LiM. GRAPHIC exploits content-addressable memory (CAM) and row-wise-accessible SRAM. By providing the in-situ, full-parallelism, and low-overhead operations of address search, cache read-compute-and-update, GRAPHIC accomplishes high-efficiency gather and aggregation with high parallelism, high energy efficiency, low latency, and low area overheads. Experiments in both continuous data access and irregular data pattern applications show an average speedup of 5x over iso-area AVX-like LiM, and 3-5x over the emerging CAM-based accelerators of CAPE and GaaS-X in advanced techniques.
A Robustly Optimized Long Text to Math Models for Numerical Reasoning On FinQA
Renhui Zhang,Youwei Zhang,Yao Yu +2 more
TL;DR: This paper presents the approach to tackle the task objective by developing models with different specialized capabilities and fusing their strength and achieves the 1st place in FinQA challenge.