Yang Wei Lim
Universiti Putra Malaysia
8 Papers
5 Citations
Yang Wei Lim is an academic researcher from Universiti Putra Malaysia. The author has contributed to research in topics: Standard cell & Computer science. The author has an hindex of 2, co-authored 5 publications.
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Papers
Reduced hardware architecture for energy-efficient IoT healthcare sensor nodes
Yang Wei Lim,S.B. Daas,Shaiful Jahari Hashim,Roslina Mohd Sidek,Noor Ain Kamsani,Fakhrul Zaman Rokhani +5 more
- 01 Sep 2015
TL;DR: A reduced hardware architecture system-on-chip targeting digital block design was proposed higher energy efficiency and achieved reduction up to 24% of leakage power and 15% of dynamic power reduction over reference design.
Development of automated standard cell library characterization (ASCLIC) for nanometer system-on-chip design
Muhammad Syafiq Izzat bin Hussin,Yang Wei Lim,Noor Ain Kamsani,Shaiful Jahari Hashim,Fakhrul Zaman Rokhani +4 more
- 01 Dec 2017
TL;DR: ASCLIC available as a web service that offers same function as another standard cell characterization, simply upload netlist, model if available and configurations and the results will be emailed back to the user.
Generating power-optimal standard cell library specification using neural network technique
S. H. Lim,Yang Wei Lim,S. Mashohor,Noor Ain Kamsani,Roslina Mohd Sidek,Shaiful Jahari Hashim,Fakhrul Zaman Rokhani +6 more
- 01 Oct 2017
TL;DR: A framework to select a standard cell library that can result in near-optimal power while satisfying targeted frequency is presented and the experimental result based on various synthesized benchmark circuits demonstrated the effectiveness of proposed framework.
An Ultra Low Voltage Energy Efficient Level Shifter With Current Limiter and Improved Split-Controlled Inverter
Chao Wang,Yang Wei Lim,Yuxin Ji,Jiajie Huang,Wangzilu Lu,Fakhrul Zaman Rokhani,Yehea Ismail,Yongfu Li +7 more
TL;DR: An improved ultra-low voltage energy-efficient level shifter with current limiter and improved split-controlled inverter achieves significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP) compared to prior works.
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Six-track multi-finger standard cell library design for near-threshold voltage operation in 130 nm complementary metal oxide semiconductor technology
Yang Wei Lim,Noor Ain Kamsani,Roslina Mohd Sidek,Shaiful Jahari Hashim,Fakhrul Zaman Rokhani +4 more
TL;DR: A six-track standard cell library with a multi-finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near-threshold operation and is optimised by using the parasitic effects of the technology and optimising the layout.
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