This work focuses on the accuracy and numerical strategies for solving the fractional Chaffee–Infante (CIE) equation in (2+1) dimensions computationally. This model illustrates the flow and transformation of gas as it travels through a homogeneous medium. When the constituents of a medium do not alter from their initial state, we say that the medium is homogeneous. In none of the solutions did we change the proportions of the individual components. Three novel analytical and numerical techniques provide new, dependable approaches for determining and estimating responses. The tabular data shown here facilitates interpreting the numerical data presented below. The simulations, which are exhibited in both 2D and 3D, depict the behavior of a solitary solitaire in both the natural and digital worlds. These findings demonstrate that this strategy is the most effective way to solve nonlinear mathematical physics problems. 

Plenty of accurate novel solitary wave solutions of the fractional Chaffee–Infante equation

The transmission characteristics of the printed circuit board (PCB) ensure signal integrity and support the entire circuit system, with impedance matching being critical in the design of high-speed PCB circuits. Because the factors affecting impedance are closely related to the PCB production process, circuit designers and manufacturers must work together to adjust the target impedance to maintain signal integrity. Five machine learning models, including decision tree (DT), random forest (RF), extreme gradient boosting (XGBoost), categorical boosting (CatBoost), and light gradient boosting machine (LightGBM), were used to forecast target impedance values. Furthermore, the Optuna algorithm is used to determine forecasting model hyperparameters. This study applied tree-based machine learning techniques with Optuna to predict impedance. The results revealed that five tree-based machine learning models with Optuna can generate satisfying forecasting accuracy in terms of three measurements, including mean absolute percentage error (MAPE), root mean square error (RMSE), and coefficient of determination (R2). Meanwhile, the LightGBM model with Optuna outperformed the other models. In addition, by using Optuna to tune the parameters of machine learning models, the accuracy of impedance matching can be increased. Thus, the results of this study suggest that the tree-based machine learning techniques with Optuna are a viable and promising alternative for predicting impedance values for circuit analysis.

/pdf/tree-based-machine-learning-models-with-optuna-in-predicting-2z3qqk7b.pdf

Tree-Based Machine Learning Models with Optuna in Predicting Impedance Values for Circuit Analysis

Impact of TSV bump and redistribution layer on crosstalk delay and power loss

Through-silicon-via (TSV)-based coaxial line techniques can reduce the high-frequency loss due to the low resistivity in the silicon substrate and thus can improve the efficiency of vertical signal transmission. Moreover, a TSV-based coaxial structure allows easily realizing the impedance matching in RF/microwave systems for excellent electrical performance. However, due to the limitations of existing available dielectric materials and the difficulties and challenges in the manufacturing process, ideal coaxial TSVs are not easy to obtain, and thus, the achieved electrical performance might be unexpected. In order to increase the flexibility of designing and manufacturing TSV-based coaxial structures and to better evaluate the fabricated devices, modeling and analysis theories of the corresponding high-frequency electrical performance are proposed in the paper. The theories are finally well validated using the finite-element simulation results, hereby providing guiding rules for selecting materials and improving manufacturing techniques in the practical process, so as to optimize the high-frequency performance of the TSV structures.

/pdf/electrical-characterization-of-through-silicon-via-based-3d48ilg8.pdf

Electrical Characterization of Through-Silicon-via-Based Coaxial Line for High-Frequency 3D Integration (Invited Paper)

This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end and differential signal) by using a coplanar wave guide (CPW) testing structure. These results, based on traditional TSV arrays, show that a staggered TSV layout with differential signals had lower crosstalk noise. On this basis, the octagonal layout of TSV array is proposed and we show that it has obvious superiority in reducing occupied silicon area and crosstalk noise. Compared with traditional TSV arrays, the crosstalk noise is almost reduced by 44%. In order to further reduce the silicon area occupied by TSV without worsening crosstalk noise, the new division TSV structure is proposed in which a large TSV was substituted by four smaller TSVs. The area occupied by a single TSV and TSV array are both reduced by 60% without decreasing signal integrity when the regular TSV in the octagonal layout are replaced by a new TSV structure.

https://www.mdpi.com/2227-9717/10/2/260/pdf?version=1643361068

Crosstalk Noise of Octagonal TSV Array Arrangement Based on Different Input Signal

With the application of heterogeneous integration and advanced packaging technologies, the use of through-silicon vias (TSVs) to deliver the power supply has become popular in the design of stacked chips in three-dimensional integrated circuits. High-density vertical interconnections offer higher speed and bandwidth, but the electromagnetic coupling effect among TSVs becomes more serious. Therefore, investigation of the noise coupling among TSVs and analysis of its impact on the power supply become important considerations. An analytical model based on the theory of multiconductor transmission lines (MTLs) is presented herein to discuss such TSV noise coupling. The method can accurately and quickly estimate the noise coupling coefficient among a large number of TSVs and offers good practicability for similar structures and even the TSVs of complex structures. Further, the influence of TSV noise coupling and simultaneous switching noise from switching circuits on the supplied power voltage is discussed. Finally, the parameters of an actual Intel chip are taken as an example to analyze the supplied power voltage that reaches complementary metal–oxide–semiconductor (CMOS) circuits through the three-dimensional (3D) power distribution network after considering the power supply noise. The presented model is validated by comparing the calculation results with those obtained from a full-wave simulator. The runtime and memory consumption requirements are lower than those of the full-wave simulator.

MTL-based modeling and analysis of the effects of TSV noise coupling on the power delivery network in 3D ICs

A numerical study of shock-interface interaction and prediction of the mixing zone growth in inhomogeneous medium

Interposer and chiplet-based 2.5-D integrated circuit (IC) designs have become a new trend for block-level heterogeneous integration. In this paper, a new hybrid metaheuristic algorithm named Metropolis-based differential particle swarm optimization (MDP) is designed to jointly optimize the multiconstraints and impedance-based hybrid objective function of chiplet-based 2.5-D IC including interposers, chiplets, through-silicon via (TSV) arrays, bumps, and metal-insulator-metal (MIM) capacitors for simultaneous switch noise (SSN) reduction. Combined with the cascaded PDN assembly method, constraints on routing, delay and proximity distance between the entire system and an impedance-oriented function with multiple critical factors, a hybrid objective function with respect to the 2.5-D PDN is obtained. Integrating the advantages of multiple algorithms, a better hybrid MDP algorithm is designed to optimize the proposed key function. This method adopts the Metropolis rule to avoid the waste of the update mechanism for out-of-boundary particles. The placement, orientation of the chiplets, the on-interposer decoupling capacitor and the constraints of the 2.5-D system are co-optimized to find the optimal solution to eliminate the SSN. The overdesign of the system, different target impedance, different objective-oriented circuit optimization schemes and trade-offs in different constraints are also discussed carefully in this paper for 2.5-D ICs.

Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination

An accurate impedance modeling of a multi-stacked on-chip power distributed network (PDN) based on through-silicon-vias (TSVs) is vitally important to estimate the electrical performance in three-dimensional integrated circuits (3D ICs). This paper proposes a method for calculating the impedance matrix of the multi-stacked on-chip PDN, which mainly consists of arbitrarily distributed TSVs and grid-type on-chip PDNs. First, a real stack-up structure of a multi-stacked on-chip PDN is separated into discrete components intentionally. Then, the equivalent lumped circuit models of all discrete components are assembled into a whole to build the transmission matrix of the multi-stacked on-chip PDN through the relationship between the nodal voltage and the nodal current. Finally, the impedance matrix can be derived through the transmission matrix. In this paper, the coupling of the arbitrarily distributed TSVs and the distributional effect of the on-chip PDN are considered in the impedance matrix through the transmission matrix method (TMM). The proposed method replaces the simulation of the complex equivalent circuit model with the matrix calculation. The verification results show that the deviation of resonant frequency is about 6 $$\%$$ and the conversation of the simulation time is about 99.9 $$\%$$ compared with the HFSS model. It can accurately and quickly calculate the impedance of the multi-stacked on-chip PDN. 

/pdf/impedance-modeling-and-analysis-of-multi-stacked-on-chip-1ka7a0cd.pdf

Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

With the ever-increasing integration density of electronic systems and reduced noise margins, maintaining high power integrity has become a formidable challenge in the design of high-performance 3-D integrated circuits (3D ICs). To enhance power integrity, the insertion of decoupling capacitors (decaps) has proven to be an important and effective solution. However, existing decoupling capacitor optimization approaches, while meeting constraints on input impedance, suffer from a significant overdesign issue. This article proposes a novel trade-off optimization method for decoupling capacitor assignment in interposers to address power integrity concerns. The method utilizes an immune algorithm (IA) to minimize the cost of decoupling capacitors while adhering to constraints on impedance bounds and avoiding over-design. The key enabler for achieving efficient optimization lies in the estimation of the required decoupling capacitor count so that the scope of the search space has been significantly reduced. The proposed method achieves a reduction in decoupling capacitor cost, while also exhibiting a speedup compared to other methods.

Analysis and Design of the Interposer PDN With Optimal Arrangement of Decoupling Capacitors

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