The invention discloses a Cache data processing method and a Cache. The cache data processing method comprises the steps that a Cache receives address information, sent by a CPU, of a Main memory, andthe address of the Main memory comprises a Main memory Tag field and a Cache set index field; the Cache searches a Loop table according to the Main memory Tag field so as to obtain a mapping offset value; the Cache adds the mapping offset value and the value of the Cache set index field so as to obtain a line address of the Cache; the Cache reads the Cache memory Tag stored in the line address, aand compares the Main memory Tag field with the Cache memory Tag, and if the Main memory Tag field is consistent with the Cache memory Tag, outputting the data stored in the line address to the CPU by the Cache. According to the Cache data processing method and the Cache, the side channel attack based on the Cache access time can be effectively avoided, the hardware implementation is simple, andthe CPU operation efficiency is not greatly influenced.

Cache data processing method and Cache

A Gaussian sampling circuit resistant to simple power consumption analysis attacks. The Gaussian sampling circuit comprises: a control module, a random number generation module, a binary comparison module, a first single-port RAM, a sampling result output module and a power consumption information concealing module, wherein the control module is used for controlling the state transition and enabling of the circuit; the random number generation module generates uniformly distributed random numbers by means of a shift register; the binary comparison module locates, by means of a binary search algorithm, addresses of the random numbers in a distribution cumulative function table with a Gaussian distribution; the sampling result output module performs a modulus operation on the located addresses to form sampling outputs; and the power consumption information concealing module generates a random power consumption by means of searching, in a binary manner, for the addresses of the random numbers in a pseudo-distribution cumulative function table. According to the Gaussian sampling circuit composed of same, power consumption information during a sampling process can be effectively concealed, and the characteristic of resistance to selective-input simple attack analysis is realized.

Gaussian sampling circuit resistant to simple power consumption analysis attacks

The invention discloses a safety reconfigurable framework capable of resisting power dissipation attack, which comprises a multi-line reconfigurable array operation line, a line controller, a general register file, a register, an input cache, an output cache, a reconfigurable search table, a first multichannel data selector, a secret share safety protection module and a data path dynamic reconfiguration safety protection module, wherein the reconfigurable search table comprises an arithmetical logic unit, a data replacing network, a data loading unit and a data output unit; the secret share safety protection module comprises a second multichannel data selector, an XOR operation module, a data cache module and a first random number generator; the data path dynamic reconfiguration safety protection module comprises a third multichannel data selector, a fourth multichannel data selector, a second random number generator, a third random number generator, a first delay data channel and a second delay data channel. The safety reconfigurable framework has advantages of guaranteeing safety while greatly reducing area and performance cost.

Safety reconfigurable framework capable of resisting power dissipation attack

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Safety reconfigurable framework capable of resisting power dissipation attack