The invention provides an electronic equipment awakening method which comprises the following steps of: acquiring a test voice set, and extracting a corresponding test voice feature set through a first neural network in a voice processing model; determining a corresponding test feature based on the test voice feature set through a first neural network in the sound processing model; acquiring a wake-up voice feature set, and extracting corresponding wake-up word features through the first neural network in the sound processing model; and carrying out wake-up judgment through a second neural network in the sound processing model according to the test features and the wake-up word features. Thereby, on the basis of the result of the wake-up judgment, the task matched with the wake-up voice features can be executed through the electronic equipment, the calculation complexity is effectively reduced, the response speed is improved, the wake-up performance of the electronic equipment is improved, the application scene of a wake-up scheme is expanded, and the robustness and generalization ability of the sound processing model are improved.

Electronic equipment awakening method and device, electronic equipment and storage medium

Disclosed is a convolutional neural network oriented two-phase coefficient adjustable analog multiplication calculation circuit, belonging to the technical field of calculation, reckoning, and counting. The multiplication calculation circuit comprises a current-mode network digital-to-analog conversion module, a two-phase coefficient adjustable analog multiplication array, a pipeline analog-to-digital conversion module, and a calculation unit control module. The multiplication calculation of a neural network layer is realized by using a discrete time circuit structure, and a signed multiplier design is newly added so as to provide positive control and negative control, such that the multiplication of signed bits can be realized, and a wider range of voltage amplitudes can be provided.

Convolutional neural network oriented two-phase coefficient adjustable analog multiplication calculation circuit

A method for selecting a calculation bit width of a multi-bit width processing element (PE) array and a calculation precision control circuit. A probability value outputted by a last Softmax layer of a neural network is analyzed to determine the magnitude of the outputted maximum probability so as to evaluate network recognition precision; and it is determined, by means of two set probability thresholds, whether the outputted maximum probability value satisfies the requirement of calculation precision, wherein if the maximum probability value is less than the minimum threshold, a signal of a high bit width PE array is used, if the maximum probability value is greater than the minimum threshold and less than the maximum threshold, the previous bit width PE array is maintained, and if the maximum probability value is greater than the maximum threshold, a signal of a low bit width PE array is used, so that the maximum probability outputted by the network is maintained within a certain range, thereby reducing power consumption while ensuring the recognition precision of the network.

Method for selecting calculation bit width of multi-bit width pe array and calculation precision control circuit

Disclosed in the present invention is a hybrid precision storage-based deep neural network accelerator, belonging to the technical field of calculation, estimation and counting. The accelerator comprises an on-chip cache module, a control module, a multiplication and addition batch calculation module having a controllable bit width, a non-linear calculation module, a register array and a dual lookup table-based Huffman decoding module. Significant bit and sign bit parameters of weights are stored in the same memory, so that data storage and analysis of hybrid prediction are realized, and multiplication and addition operations of data and weights of hybrid precision are realized. By means of the hybrid precision-based data storage and analysis and the dual lookup table based Huffman decoding, the compression and storage of data and weights at different precisions are realized, reducing the data flow, and realizing deep neural network-based data scheduling of low power consumption.

Hybrid precision storage-based depth neural network accelerator

The invention provides a data processing method and device, a photonic neural network chip and a data processing circuit. The data processing method can be applied to a photonic neural network chip. The method comprises the steps of obtaining a highest-order calculation result of a product of a multiplicand and a multiplier; judging whether the highest-order calculation result meets the precisionrequirement or not according to the precision requirement of the data processing model; if the highest-order calculation result does not meet the precision requirement, accumulation of the highest-order calculation result and subsequent high-order calculation results is carried out until the accumulation result meets the precision requirement or accumulation of all the calculation results is completed. According to the technical scheme provided by the embodiment of the invention, the calculation efficiency of the photonic neural network chip can be further improved.

Data processing method and device, photonic neural network chip and data processing circuit

The invention discloses a deep neural network accelerator based on hybrid precision storage, and belongs to the technical field of calculation, reckoning and counting. The accelerator comprises an on-chip cache module, a control module, a bit-width-controllable multiply-add-batch calculation module, a nonlinear calculation module, a register array and a Huffman decoding module based on double lookup tables, effective bit and sign bit parameters of the weight are stored in the same memory, so that mixed-precision data storage and analysis are realized, and multiply-add operation of mixed-precision data and weight is realized. Through data storage analysis based on mixed precision and Huffman decoding based on a dual lookup table, compression and storage of data and weights under different precision are realized, data streams are reduced, and low-power-consumption data scheduling based on a deep neural network is realized.

Deep neural network accelerator based on hybrid precision storage

The invention provides a keyword recognition system based on a hybrid compression convolutional neural network, and belongs to the technical field of calculation, reckoning and counting. The system comprises an analog-to-digital conversion module, a feature extraction module and a hybrid compression convolutional neural network module. An input value of the convolutional neural network is subjected to high-order residual quantization, a weight value of the neural network is subjected to fine-grained progressive quantization and low-bit quantization of an activation value, and then a convolution kernel is subjected to pruning based on a front and back stage joint evaluation strategy, so that the parameter quantity and the model size of the network are reduced. The parameter quantity of theneural network is reduced through quantization, and the calculation amount of the network is reduced through pruning, so that the purpose of optimizing the network is achieved.

Keyword recognition system based on hybrid compression convolutional neural network

The invention discloses a selection method for calculating bit width of a multi-bit-width PE array and a calculation precision control circuit, and belongs to the technical field of calculation, reckoning and counting. According to the invention, the output probability value of the last Softmax layer of the neural network is analyzed to judge the output maximum probability so as to evaluate the network identification precision; whether the output maximum probability value meets the calculation precision requirement or not is judged through two set probability thresholds; if the maximum probability value is smaller than the minimum threshold value, the signal of the high bit width processing element array is adopted; if the maximum probability value is larger than the minimum threshold value and smaller than the maximum threshold value, the previous bit width processing element array is maintained, and if the maximum probability value is larger than the maximum threshold value, the signal of the low bit width processing element array is adopted, the maximum probability output by the network is maintained in a certain atmosphere, and the power consumption is reduced while the identification precision of the network is ensured.

Selection method for calculating bit width of multi-bit-width PE array and calculation precision control circuit

The invention discloses a double-phase coefficient adjustable analog multiplication calculation circuit for a convolutional neural network, and belongs to the technical field of calculation, reckoningand counting. The multiplication calculation circuit comprises a current type network digital-to-analog conversion module, a double-phase coefficient adjustable analog multiplication array, a pipelined analog-to-digital conversion module and a calculation unit control module, a discrete time circuit structure is adopted to achieve multiplication calculation of a neural network layer, signed multiplier design is newly added to provide forward control and negative control, multiplication with sign bits can be achieved, and voltage amplitude in a wider range is provided.

Double-phase coefficient adjustable analog multiplication calculation circuit for convolutional neural network

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