Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Integrated circuit device and method of manufacturing the same

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Up to 2/spl times/ improvement in SNM can be achieved in 6-T FinFET-based SRAM cells. A 4-T FinFET-based SRAM cell with built-in feedback can achieve sub-100pA per-cell standby current and offer the similar improvements in SNM as the 6-T cell with feedback, making them attractive for low-power, low-voltage applications.

FinFET-based SRAM design

Important physical insights regarding the design and performance of independent-gate FinFETs, e.g., the MIGFET , are gained from measured data and predictions from our process/physics-based double-gate (DG) MOSFET model (UFDG) in Spice3. Inversion charge-centroid shifting, modulated by gate biases as well as by quantum-confinement and short-channel effects, underlies the sensitivity of the MIGFET (front-gate) threshold voltage to the back-gate bias. MIGFET design and operation-mode options are examined for optimizing circuit applications. Further, novel design of a single-device RF mixer and a double-balanced counterpart using MIGFETs is studied with UFDG/Spice3. Reasonably good MIGFET mixers, with regard to conversion gain and linearity with small-size/low-voltage/low-power requirements, can be achieved with optimal biases on the two gates and good design of the MIGFET structure.

Physical insights regarding design and performance of independent-gate FinFETs

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

A double gate semiconductor device ( 2006 ) is used beneficially as a multiplier ( 2000 ). The double gate semiconductor device ( 2006 ) has a lateral fin ( 105 ) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure ( 2106 ) with alternating source/drain terminals ( 2120, 2122, 2124, 2126 ) in which the sources are connected together and the drains are connected together. Gates ( 2116, 2110 ) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier ( 2000 ) may also be used as a mixer and further as a phase detector.

Method and circuit for multiplying signals with a transistor having more than one independent gate structure

We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO/sub 2/ dielectric with elevated Source/Drain (SD) extensions As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20/spl Aring/ The intrinsic low-leakage nature of the FDSOI device and it's immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits

Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions

A semiconductor device (151) is provided which comprises (a) a semiconductor substrate (103); (b) a fin (109) comprising a semiconductor material and being in electrical contact with the substrate; (c) a first floating gate (121) disposed on a first side of said fin; and (d) a control gate (107).

Vertical transistor NVM with body contact structure and method

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