Yanfei Chen
Fujitsu
25 Papers
261 Citations
Yanfei Chen is an academic researcher from Fujitsu. The author has contributed to research in topics: CMOS & Successive approximation ADC. The author has an hindex of 10, co-authored 25 publications. Previous affiliations of Yanfei Chen include Keio University.
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Papers
Split capacitor DAC mismatch calibration in successive approximation ADC
Yanfei Chen,Xiaolei Zhu,Hirotaka Tamura,Masaya Kibune,Yasumoto Tomita,Takayuki Hamada,Masato Yoshioka,Kiyoshi Ishikawa,Takeshi Takayama,Junji Ogawa,Sanroku Tsukamoto,Tadahiro Kuroda +11 more
- 09 Oct 2009
TL;DR: A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch and a comparator with digital timing control offset cancellation is proposed.
148
22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI
Yanfei Chen,Masaya Kibune,Asako Toda,Akinori Hayakawa,Tomoyuki Akiyama,Shigeaki Sekiguchi,Hiroji Ebe,Nobuhiro Imaizumi,Tomoyuki Akahoshi,Suguru Akiyama,Shinsuke Tanaka,Takasi Simoyama,Ken Morito,Takuji Yamamoto,Toshihiko Mori,Yoichi Koyanagi,Hirotaka Tamura +16 more
- 19 Mar 2015
TL;DR: A hybrid integrated electrical-optical (E-O) interface including a driver/TIA chip in 28nm CMOS and a modulator/PD chip in SOI, based on a mixed-pitch bumping technology is presented, promising a disruptive alternative for next-generation scalable data centers.
70
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS
Takayuki Shibasaki,Win Chaivipas,Yanfei Chen,Yoshiyasu Doi,Takayuki Hamada,Hideki Takauchi,Toshihiko Mori,Yoichi Koyanagi,Hirotaka Tamura +8 more
- 10 Jun 2014
TL;DR: A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS and sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front- end and reduces the power consumption.
59
A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects
Akinori Hayakawa,Masaya Kibune,Asako Toda,Shinsuke Tanaka,Takasi Simoyama,Yanfei Chen,Tomoyuki Akiyama,Shigekazu Okumura,Takeshi Baba,Tomoyuki Akahoshi,Seiji Ueno,Kazunori Maruyama,Masahiko Imai,Jian Hong Jiang,Pradip Thachile,Tamer Riad,Shigeaki Sekiguchi,Suguru Akiyama,Yu Tanaka,Ken Morito,Daisuke Mizutani,Toshihiko Mori,Takuji Yamamoto,Hiroji Ebe +23 more
- 22 Mar 2015
TL;DR: A novel configuration of hybrid-integrated silicon photonic interconnects employing a bridge structure is presented, and 25 Gbps error-free operation between transmitter and receiver with power efficiency of 9.6 mW/Gbps including a serializer chip is demonstrated.
18
Patent
Ad converter circuit and ad conversion method
Masato Yoshioka,Yanfei Chen,Ide Tatsuya +2 more
- 24 Apr 2013
TL;DR: In this paper, a low-power and high-speed ADC with a fixed-quantity change-time measurement converter is presented, where the residual voltage is changed at a fixed rate of change and the time until a predetermined value is reached.
18