The invention provides a shuffled frog-leaping based division method of software and hardware. The method comprises the steps of determining the maximum iterations of the algorithm at the initial; calculating the area and time cost of the hardware in the corresponding software and hardware division scheme corresponding to each frog; descending and sequencing the whole frog group according to the adaptive fitness of individual fog; updating the fog groups in each group at a plurality of times to enable the adaptive fitness of the worst frog in the group to be prior to that of the previous frog as well as meeting the system limitation condition; updating the optimal frog in the group by the random updating method in case of failing to update; shuffling the whole frog groups; finding the global optimal solution as the optimal software and hardware division scheme after the iteration is done. According to the method, the sub-task of one embedded composite system is divided through a processor, and meanwhile, the searching and the optimizing capacity of the system are improved; the optimal software and hardware division scheme can be found, and as a result, the task performing efficiency of the system can be increased.

Shuffled frog-leaping based division method of software and hardware

The invention discloses an electronic design automation (EDA) comprehensive experiment platform The technology of circuit dynamic restructuring is adopted in an EDA comprehensive experiment platform, random connection among all resources of the whole EDA comprehensive experiment platform is achieved, common digital logic chip is imitated, and experiment contents with various types and various difficulties are provided The EDA comprehensive experiment platform is capable of achieving independent foundations of a digital circuit and logic design, a programmable logic device and a singlechip, improving the experiment contents, and completing comprehensive designed experiments of courses At the same time, according to the requirements of the courses, the EDA comprehensive experiment platform is capable of flexibly designing the experiment contents with various types and various difficulties Furthermore, except for common experiment peripheral resources, the EDA comprehensive experiment platform is provided with a signal generating module and a signal measuring module and capable of generating square signals with tunable frequency and measuring frequency and voltage of input signals

Circuit dynamic restructuring electronic design automation (EDA) comprehensive experiment system

The invention provides an efficient dynamic division method of software and hardware, and aims at designing an embedded system. The method comprises the steps of 1) building an accurate mathematic model for software and hardware division problem; 2) simplifying the accurate mathematic model into a low-dimensional simple model according to the relevance of coefficients of a coefficient matrix in a limitation condition; 3) solving the simplified model obtained in step 2) through the automatic division algorithm to obtain the optimal software and hardware division scheme, recording the algorithm solving operation time, and observing the simplified mode solving efficiency of the automatic division algorithm; 4) verifying the feasibility of the software and hardware division scheme; 5) outputting the optimal software and hardware division scheme. With the adoption of the method, the complexity of the model can be reduced; the model solving time of the automatic division algorithm can be greatly reduced; the division algorithm solving efficiency can be increased; the large scale software and hardware can be particularly quickly divided; therefore, large scale complex software and hardware can be divided, and the applicable scope of the model is expanded.

Efficient dynamic division method of software and hardware

The invention discloses an agreement inventory material order allocation method based on greedy algorithm, comprising a data import and export unit, an information query and display unit, a material allocation unit and an information maintaining unit. An excel sheet downloaded by ERP (Enterprise Resource Planning) is imported into a software database through a data import and export unit, corresponding planned batches and allocation modes are selected and allocation is executed in the material allocation unit, moreover, allocation result and information of unallocated material can be checked in the information query and display unit. According to the invention, four agreement inventory material allocation modes suitable for the material allocation needs of power supply companies are set, the modes are realized through a software unit, planned allocation of material is carried out automatically through importing ERP and material planning data, and thus, efficiency of material allocation of the power supply companies is improved.

Agreement inventory material order allocation method based on greedy algorithm

The invention discloses a reconfigurable electronic design automation (EDA) experimental platform, and relates to an EDA experimental platform. The reconfigurable EDA experimental platform comprises a core processing unit and a peripheral circuit. The core processing unit comprises a master processing field-programmable gate array (FPGA) chip and a slave processing FPGA chip, which are directly interconnected. The peripheral circuit comprises a main memory, a liquid crystal display (LCD) interface circuit, a light-emitting diode (LED) interface circuit, a keyboard interface circuit, a mouse interface circuit, a serial peripheral interface (SPI) circuit, a network cable interface, an analogue/digital (A/D) interface chip, two configuration storage chips, a joint test action group (JTAG) interface circuit and the like. Functions of the reconfigurable FPGA chips are reconstructed, so that the requirements of application places of an embedded experimental platform, a digital signal processor (DSP) experimental platform and an FPGA experimental platform on application characteristics of the experimental platform can be met respectively, and an application range is widened; and a plurality of experimental contents can be combined on the same experimental platform for experiments and training, so that the experimental platform purchasing cost of a user is lowered, and the application efficiency of the experimental platform is improved.

Reconfigurable electronic design automation (EDA) experimental platform

The utility model relates to a portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board which comprises a universal serial bus interface, a drive circuit module, an electrically-erasable module, a communication/downloading module, a frequency adjustable clock module, a dial switch module, a field programmable gate array, a pulse switch module, a diode display module and a nixie tube display module. The drive circuit module connected with the universal serial bus interface is in two-way connection with the electrically-erasable module and the communication/downloading module respectively, the communication/downloading module is in two-way connection with field programmable gate array and the frequency adjustable clock module, the frequency adjustable clock module, the frequency adjustable clock module and the pulse switch module are all connected with the field programmable gate array, and the field programmable gate array is also connected with the diode display module and the nixie tube display module. The universal serial bus interface integrates a power supply, downloading and communication, and a communication function module enables the portable universal digital logic design and EDA comprehensive experimental board to carry out data interaction on other universal microcontrollers as a coprocessor.

Portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board

A hardware-software partitioning method based on a greedy simulated annealing algorithm comprises the following steps: (1) specifying the hardware-software partitioning problem as 0-1 knapsack problem, initially partitioning a task set by a greedy algorithm with low time complexity, and setting the partitioning result as the initial value of the simulated annealing algorithm; and (2) performing the simulated annealing algorithm, which is mainly composed of two layer loops, namely an inner loop and an outer loop, wherein the inner loop can generate a new partition according to a disturbance model, and determine and accept the new partition according to an acceptance criteria; and the outer loop is used for determining whether or not to exit the loop process according to a temperature threshold and the number of new partitions which are not accepted continuously. The method provided by the invention can reduce algorithm operation time, improve search quality and reduce calculation complexity.

Hardware-software partitioning method based on greedy simulated annealing algorithm

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Portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board

Hardware-software partitioning method based on greedy simulated annealing algorithm