A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage (V/sub th/) depends on the concentration of nitrogen in the TiNx gate electrode. We found that a V/sub th/ shift as high as -110 mV is controlled by low-energy nitrogen-ion implantation (N I/I) into the titanium nitride film. By using this technology only for nMOSFETs, dual-metal gate CMOS devices are fabricated with a CMOS-process compatibility. A low V/sub th/ is achieved for both n- and pMOSFETs by combining N I/I and a low-doped channel structure.

A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 /spl Aring/ oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 /spl mu/m technology node, this structure could be scaled to EOT=12 /spl Aring/ if the maximum allowed gate leakage current is 1 A/cm/sup 2/ and EOT=9 /spl Aring/ if the maximum allowed gate leakage current is 100 A/cm/sup 2/.

Investigation of hole-tunneling current through ultrathin oxynitride/oxide stack gate dielectrics in p-MOSFETs

A novel dual-metal gate CMOS technology using ni- trogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage ( ) depends on the con- centration of nitrogen in the TiNx gate electrode. We found that a shift as high as 110 mV is controlled by low-energy ni- trogen-ion implantation (N I/I) into the titanium nitride film. By using this technology only for nMOSFETs, dual-metal gate CMOS devices are fabricated with a CMOS-process compatibility. A low is achieved for both n- and pMOSFETs by combining N I/I and a low-doped channel structure.

A Dual-Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-/spl mu/m and a 0.1-/spl mu/m technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I/sub b,peak/ is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.

Projecting lifetime of deep submicron MOSFETs

In this paper, a 0.15 /spl mu/m embedded DRAM technology is described which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-function gate with Si/sub 3/N/sub 4/ capped Ti polycide, and selective Co silicidation of source/drain diffusion by Si/sub 3/N/sub 4/ liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-aligned contact (SAC) etching. Low temperature Al/sub 2/O/sub 3/ stacked cell capacitor with hemispherical grain (HSG) makes it possible to realize the sufficient storage capacitance in DRAM arrays and the high performance transistor. The CMP planarization of interlayer dielectric enlarges the depth of focus for lithography and enables the multilevel metallization. These integration technologies can be fairly extendible to the future embedded DRAM in 0.13 /spl mu/m technology node and beyond.

A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 /spl mu/m technology node and beyond

In this paper, we have investigated the performance and reliability of dual-gate (N/sup +/-poly for NMOS and P/sup +/-poly for PMOS) CMOS devices with gate oxides grown on nitrogen Implanted Si substrates (NISS). Oxynitride gate dielectrics (28/spl sim/63 /spl Aring/) were fabricated with several nitrogen implantation doses and compared with control SiO/sub 2/ of identical thicknesses. Our results indicate that as gate oxide thickness is scaled down, NISS oxides show improvements over control SiO/sub 2/ in maximum transconductance, subthreshold swing, as well as on- and off-state drain current for both N- and PMOSFETs. Hot-carrier stressing is performed on both NISS and control devices of identical gate oxide thickness (36 /spl Aring/). Compared to control SiO/sub 2/, NISS oxide devices show longer device lifetime and suppressed gate-induced drain leakage (GIDL) current for PMOSFETs under I/sub g,max/ stressing. No difference in NMOSFET degradation (/spl Delta/V/sub t/, /spl Delta/G/sub m/) is observed under I/sub sub,max/ stressing. However, significant degradation under hot hole injection (V/sub g/=V/sub d/) compared to control SiO/sub 2/ is observed in NISS P/sup +/-poly PMOSFETs. In addition, degradation of NISS oxide TDDB is observed.

Performance and reliability assessment of dual-gate CMOS devices with gate oxide grown on nitrogen implanted Si substrates

A significant degradation under hot-hole injection is observed in P/sup +/-poly PMOSFETs with oxynitride gate dielectrics. Both oxynitrides formed by gate oxide grown on Nitrogen Implanted Si Substrates (NISS) and NO-annealed SiO/sub 2/ oxynitride gate dielectrics are used and compared to control SiO/sub 2/ gate dielectrics of identical thicknesses. A physical model responsible for such enhanced degradation in PMOSFETs with oxynitride gate dielectric is proposed. It is shown that the hole injection barrier lowering as a result of the nitrogen-rich layer at the SiO/sub 2//Si interface in oxynitride is responsible for such enhanced degradation.

Enhanced hot-hole degradation in P/sup +/-poly PMOSFETs with oxynitride gate dielectrics

In this paper, a significant degradation under hot hole injection is observed in P+ -poly PMOSFETs with oxynitride gate dielectrics. In our study, both oxynitrides formed by gate oxide grown on Nitrogen Implanted Si Substrates (NISS) and NO-annealed SiO2 oxynitride gate dielectrics are used and compared to control SiO2 gate dielectrics of identical thicknesses. A physical model responsible for such enhanced degradation in PMOSFETs with oxynitride gate dielectric is proposed. It is shown that the hole injection barrier lowering as a result of the nitrogen-rich layer at the SiO2/Si interface in oxynitride is responsible for such enhanced degradation.

Enhanced Degradation in P + -Poly PMOSFETs With Oxynitride Gate Dielectrics Under Hot-Hole Injection

This paper reports an investigation of the !f.egative-!},.ias lemperature Instability (NET!) stress in 0.3 J.lm p+ -poly PMOSFETs with gate oxides grown on !f.itrogen Implanted §J §.ubstrates (N!SS) in comparison with traditional control Si02 with identical oxide thickness of 36 A. Our results . indicate that N!SS oxides have stronger endurance to NET! degradation than control oxides.

http://ieeexplore.ieee.org/iel5/10058/32252/01503546.pdf

Study of NBTI Stress in P+-Poly PMOSFETs with Gate Oxides Grown on Nitrogen Implanted Si Substrates

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Papers

Performance and reliability assessment of dual-gate CMOS devices with gate oxide grown on nitrogen implanted Si substrates

Enhanced hot-hole degradation in P/sup +/-poly PMOSFETs with oxynitride gate dielectrics

Enhanced Degradation in P + -Poly PMOSFETs With Oxynitride Gate Dielectrics Under Hot-Hole Injection

Study of NBTI Stress in P+-Poly PMOSFETs with Gate Oxides Grown on Nitrogen Implanted Si Substrates