The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Emerging Applications for High K Materials in VLSI Technology

This paper presents a detailed analysis of the multifrequency capacitance–voltage and conductance–voltage data of $\hbox{Al}_{2}\hbox{O}_{3}/\hbox{n-InGaAs}$ MOS capacitors. It is shown that the widely varied frequency dependence of the data from depletion to inversion can be fitted to various regional equivalent circuits derived from the full interface-state model. In certain regions, incorporating bulk-oxide traps in the interface-state model enables better fitting of data. By calibrating the model with experimental data, the interface-state density and the trap time constants are extracted as functions of energy in the bandgap, from which the stretch-out of gate voltage is determined. It is concluded that the commonly observed decrease of the 1-kHz capacitance toward stronger inversion is due to the increasing time constant for traps to capture majority carriers at the inverted surface.

Interface-State Modeling of $\hbox{Al}_{2}\hbox{O}_{3}$ –InGaAs MOS From Depletion to Inversion

The III-V semiconductors such as In x Ga 1-x As (x = 0.53-0.70) have attracted significant interest in the context of low power digital complementary metal-oxide-semiconductor (CMOS) technology due to their superior transport properties. However, top-down patterning of III-V semiconductor thin films into strongly confined quasi-one-dimensional (1D) nanowire geometries can potentially degrade the transport properties. To date, few reports exist regarding transport measurement in multigate nanowire structures. In this work, we report a novel methodology for characterizing electron transport in III-V multigate nanowire field effect transistors (NWFETs). We demonstrate multigate NWFETs integrated with probe electrodes in Hall Bridge geometry to enable four-point measurements of both longitudinal and transverse resistance. This allows for the first time accurate extraction of Hall mobility and its dependence on carrier concentration in III-V NWFETs. Furthermore, it is shown that by implementing parallel arrays of nanowires, it is possible to enhance the signal-to-noise ratio of the measurement, enabling more reliable measurement of Hall voltage (carrier concentration) and, hence, mobility. We characterize the mobility for various nanowire widths down to 40 nm and observe a monotonic reduction in mobility compared to planar devices. Despite this reduction, III-V NWFET mobility is shown to outperform state-of-the-art strained silicon NWFETs. Finally, we demonstrate evidence of room -temperature ballistic transport, a desirable property in the context of short channel transistors, in strongly confined III-V nanowire junctions using magneto-transport measurements in a nanoscale Hall-cross structure.

/pdf/electron-transport-in-multigate-in-x-ga-1-x-as-nanowire-fets-fpxlp1n32r.pdf

Electron transport in multigate In x Ga 1-x as nanowire FETs: from diffusive to ballistic regimes at room temperature.

We report on the influence of variations in the process parameters of an in-situ surface cleaning procedure, consisting of alternating cycles of nitrogen plasma and trimethylaluminum dosing, on the interface trap density of highly scaled HfO2 gate dielectrics deposited on n-In0.53Ga0.47As by atomic layer deposition. We discuss the interface chemistry of stacks resulting from the pre-deposition exposure to nitrogen plasma/trimethylaluminum cycles. Measurements of interface trap densities, interface chemistry, and surface morphology show that variations in the cleaning process have a large effect on nucleation and surface coverage, which in turn are crucial for achieving low interface state densities.

/pdf/influence-of-plasma-based-in-situ-surface-cleaning-1jsjmokaww.pdf

Influence of plasma-based in-situ surface cleaning procedures on HfO2/In0.53Ga0.47As gate stack properties

Electrical characterization of top-gated molybdenum disulfide metal-oxide-semiconductor capacitors with high-k dielectrics

In this work, we propose a method to quantify the density of interfacial states at the oxide/semiconductor interface using only Hall concentration and low frequency capacitance-voltage data. We discuss the advantages of the proposed method over commonly used admittance techniques in characterizing highly disordered interfaces between the high-k dielectric and high mobility substrates. This gated Hall method is employed to characterize high-k/IIIV interface quality in metal-oxide semiconductor high electron mobility transistor structures with high mobility InGaAs channels.

Quantification of interfacial state density (Dit) at the high-k/III-V interface based on Hall effect measurements

The superior transport properties of III–V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III–V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj&#60;10nm, N D =5×1019 cm−3, ρ c = 6Ω.µm2 and Dit = 4×1012 eV−1 cm−2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.

Challenges of III–V materials in advanced CMOS logic

By combining the capacitance and conductance analysis techniques, we obtained the D it distribution throughout the band gap of In 0.53 Ga 0.47 As capacitors with H 2 O-based and O 3 -based ALD oxides. The choice of appropriate temperature to obtain the quasi-static C-V and the DC voltage sweep rate is an essential for the correct extraction of D it . Simultaneously we obtained the trap kinetics characteristics. We claim that: (i) the H 2 O-based ALD deposition results in a fewer traps in the lower portion of In 0.53 Ga 0.47 As band gap, (ii) is related to the formation of the thicker native oxide in the O 3 -based samples; (iii) the mid gap traps in the H 2 O-based samples are significantly slower than those in the O 3 -based samples, which indicate their different nature.

Interface states at high- к /InGaAs interface: H 2 O vs. O 3 based ALD dielectric

We report significant improvements in the high-k/In 0.53 Ga 0.47 As interface quality by controlling atomic layer deposition (ALD) oxidizer chemistry. A step-by-step correlation between electrical data and chemical reactions at the high-k/InGaAs interface has been established using synchrotron photoemission. AsO x , GaO x , and In 2 O 3 formed during unintentional ALD surface oxidation and the increase of As-As bonds are responsible for degrading device quality. A better quality H 2 O-based high-k gate stack is evidenced by less capacitance-voltage (CV) dispersion (14% in ZrO 2 ), smaller CV hysteresis (37% in Al 2 O 3 and 47% in ZrO 2 ), fewer border traps (Q br ) (96% in Al 2 O 3 and 25% in ZrO 2 ), and lower mean interface traps density (D it ) (91% in Al 2 O 3 and 29% in ZrO 2 ). Improvements in I d and G m therefore have been achieved by replacing O 3 with H 2 O oxidizer. Our work suggests that H 2 O-based high-k is more promising than O 3 -based high-k. These results positively impact the industry's progress toward III–V CMOS at the 11nm node.

III–V gate stack interface improvement to enable high mobility 11nm node CMOS

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Papers

Quantification of interfacial state density (Dit) at the high-k/III-V interface based on Hall effect measurements

Challenges of III–V materials in advanced CMOS logic

Interface states at high- к /InGaAs interface: H 2 O vs. O 3 based ALD dielectric

III–V gate stack interface improvement to enable high mobility 11nm node CMOS