Explanation for the appearance of alumina nanoparticles in a cold wall Atomic Layer Deposition system and their characterization

This work investigates different Al2O3-based dielectric stacks for various applications, including surface passivation of solar cells and photodetectors, replacement of SiO2 gate dielectric in advanced MOSFETs. Ultra-thin Al2O3/SiO2 (3/2 nm) stacks were deposited on silicon by using different techniques. A reference sample with only a single dry-grown SiO2 layer (3 nm) was prepared for comparison purpose. The effective carrier lifetimes were measured by the contactless photoconductance decay method. The lowest surface recombination velocity was calculated to be 34 cm/s in the Al2O3/SiO2 stack. The negative fixed charge density in the stacks was extracted from C–V characteristics. Our results reveal that the effective carrier lifetimes depend on the stacks deposition techniques and conditions, and provide a guideline for optimization.

Determination of Carrier Lifetime in Silicon Using an Ultra-thin Al 2 O 3 /SiO 2 Dielectric Stack

In this work we examine the structural and electrical properties including the memory performance of Al 2 O 3 /Si 3 N 4 /SiO 2 dielectric stacks implanted with low-energy nitrogen ions and subsequently thermal annealed at 850 or 1050 °C for 15 min. X-ray photoelectron spectroscopy reveals that the concentration and the chemical state of the nitrogen atoms within the Al 2 O 3 layer depends on the post-implantation annealing (PIA) temperature. Memory testing, performed on platinum gate capacitors, shows that charge retention of the programmed states is significantly improved for the high-temperature PIA samples as compared to the non-implanted samples. While such an improvement is not detected for the low-temperature PIA samples, the latter exhibit enhanced hole charging and thus, increased erase efficiency. Overall, our results suggest that the transport properties which control the erase and the retention characteristics of the blocking Al 2 O 3 layer can be tailored by nitrogen implantation and the PIA conditions and can be used for memory performance optimization.

Nitrogen induced modifications of MANOS memory properties

http://hub.hku.hk/bitstream/10722/202923/1/Content.pdf

Improved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory

In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25°C to 150°C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance-voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks. 

Analysis of Trap Distribution and NBTI Degradation in Al2O3/SiO2 Dielectric Stack

The authors developed a new Al2O3–SiO2 (A-O) stack for application as a high voltage complementary metal oxide semiconductor (CMOS) dielectric and/or top oxide in electrically erasable programmable read only memory floating gate and polysilicon-oxide-nitride-oxide-silicon embedded memories in advanced technology nodes. An amorphous atomic layer deposited alumina is doped with nitrogen and transformed into the crystalline phase by further rapid thermal process annealing. The 65A effective oxide thickness (EOT) stack allows operating voltages twice exceeding the values for thermal SiO2 of the same EOT, has extremely low leakage currents, has negligible charge trapping, and is immune to degradation. Moreover, after alumina removal, the remaining strongly nitrided bottom oxide layer can be used as the gate dielectric of CMOS devices.

Al2O3–SiO2 stack with enhanced reliability

Peculiarities of hole trapping in Al2O3-SiO2 gate dielectric stack

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Al2O3–SiO2 stack with enhanced reliability

Peculiarities of hole trapping in Al2O3-SiO2 gate dielectric stack