A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain is proposed. The proposed circuit can detect the alterations of clock frequency and the variations of PVT, and utilizes self-adaptive feedback loop to ensure that the circuit can achieve duty cycle correction within a wide operating frequency range. The test chip is fabricated in 130nm CMOS process, the area occupies 0.016mm2. The chip testing results indicate that the correction error is within 2% throughout the input duty cycle from 20% to 80% at the frequency from 260MHz to 1GHz. 

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

For 2D/3D image sensors, the phase and duty-cycle deviations of the modulated signal reduce depth errors. This article proposes a wide-range and high-precision phase/duty cycle correction circuit for modulation driving of 2D/3D image sensors. A self-compensating current-steering charge pump structure is proposed in the phase/duty-cycle correction circuit to minimize the current mismatch in the charge pump. In addition, a high-speed parasitic compensation (PC) circuit with an AC-coupled resistor feedback inverter is proposed to extend the correction range. The proposed correction circuit is designed with a 0.11 μm CMOS process, and its area is 0.0143 mm2. The post-simulation results show that the circuit has a wide range of phase and duty-cycle correction (−0.5 %–99.5 % and 0.4 %–98.3 %) with small accuracy errors (−0.945 %&+1.312 %, −0.875 %&1.175 %). 

Design of a wide range and high precision phase/duty-cycle correction circuit for modulation driving of 2D/3D image sensors

This paper presents an all-digital built-in-self-test (BIST) scheme to quickly test the duty cycle corrector (DCC) with de-skew circuit in NAND Flash memory. The proposed BIST circuit adopts an adjustable duty cycle module to generate the input signal of DCC, then it utilizes a high-resolution vernier time-to-digital converter to quantify the pulse widths related to duty cycle and phase difference into digital codes. The proposed BIST scheme can quickly obtain accurate measurement results of the input/output duty cycle of DCC and the phase difference of signals without using high-precision test equipment, it is a low-cost built-in testing solution for NAND Flash memory. The test chip is fabricated using 130 nm CMOS process. The area occupies 0.0425 mm2, and the proposed circuit consumes 2 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. The experimental results show that the measurement error of duty cycle is in the range of −0.85% to 1.5% and the measurement error of phase difference is within ±6 ps. 

An all-digital built-in-self-test scheme for duty cycle corrector with de-skew circuit in NAND Flash memory

This paper proposes a small-area and low-power all-digital duty cycle corrector with de-skew circuit. By adopting the proposed delay unit containing a pre-charge transistor, half cycle delay line can accurately generate half-cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high-precision clock synchronization, the proposed de-skew circuit utilizes a high-resolution two-stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz. 

https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/ell2.12793

A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.

/pdf/a-wide-range-four-phase-all-digital-dll-with-de-skew-circuit-3swom9ns.pdf

A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit

This paper presents a wide-frequency and high-precision ZQ calibration circuit for NAND Flash memory. To achieve high-precision impedance calibration within the wide frequency range of NAND Flash memory, the proposed ZQ calibration circuit adopts dynamic comparator with offset voltage compensation to accurately control the equivalent impedance of driver. And to ensure that the offset voltage of comparator can be accurately compensated in a wide frequency range, the offset voltage compensation circuit is controlled by a charge pump whose charging and discharging step time can be adjusted based on operating frequency range. The proposed circuit is fabricated in 130 nm CMOS process. In the frequency range of 1 MHz to 200 MHz, the Monte-Carlo analysis results show that the standard deviation of offset voltage is within 0.18 mV and the standard deviation of targeting calibrated impedance on 300 ohm is within 3.5 ohm. And the chip testing results show that the proposed ZQ calibration circuit can achieve 1.5% calibration accuracy. 

A wide-frequency and high-precision ZQ calibration circuit for NAND Flash memory

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