Xiaowen Chen
National University of Defense Technology
45 Papers
214 Citations
Xiaowen Chen is an academic researcher from National University of Defense Technology. The author has contributed to research in topics: Distributed shared memory & Multi-core processor. The author has an hindex of 9, co-authored 45 publications. Previous affiliations of Xiaowen Chen include Royal Institute of Technology & University of Defence.
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Papers
Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controller
Xiaowen Chen,Zhonghai Lu,Axel Jantsch,Shuming Chen +3 more
- 08 Mar 2010
TL;DR: Results show that, when the system size is scaled up, the delay overhead incurred by the controller may become less significant when compared with the network delay, and the delay efficiency of the DSM solution is close to hardware solutions on average but still have all the flexibility of software solutions.
54
Multi-bit transient fault control for NoC links using 2D fault coding method
Xiaowen Chen,Zhonghai Lu,Yuanwu Lei,Yaohua Wang,Shenggang Chen +4 more
- 01 Sep 2016
TL;DR: Comparative experiments show that the proposal can largely reduce the ECC hardware cost, have much higher fault detection coverage, maintain almost zero silent fault percentages, and have higher fault correction percentages normalized under the same area, demonstrating that it is cost-effective and suitable to the multi-bit transient fault control for NoC links.
23
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures
TL;DR: This paper proposes a novel instruction shuffle scheme that features an efficient control-flow handling mechanism and combines the best attributes of both the SIMD and MIMD execution paradigms.
12
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform
Shenggang Chen,Shuming Chen,Huitao Gu,Hu Chen,Yaming Yin,Xiaowen Chen,Shuwei Sun,Sheng Liu,Yaohua Wang +8 more
- 01 Sep 2010
TL;DR: To increase parallelism, macro block level parallelism is exploited in this paper and wave front algorithm is utilized and speedups of 13, 24, 26 and 49 are achieved for QCIF, SIF, CIF and HD sequences, respectively.
12
Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips
Xiaowen Chen,Zhonghai Lu,Axel Jantsch,Shuming Chen +3 more
- 18 Dec 2010
TL;DR: The experimental results of real applications show that the hybrid DSM organization with run-time partitioning demonstrates performance advantage over the conventional DSM counterpart, and the percentage of performance improvement depends on problem size, way of data partitioning and computation/communication ratio of parallel applications, network size of the system, etc.