Xiaolei Zhu
Keio University
11 Papers
161 Citations
Xiaolei Zhu is an academic researcher from Keio University. The author has contributed to research in topics: Comparator & Successive approximation ADC. The author has an hindex of 5, co-authored 11 publications. Previous affiliations of Xiaolei Zhu include Tsinghua University & Zhejiang University.
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Papers
Split capacitor DAC mismatch calibration in successive approximation ADC
Yanfei Chen,Xiaolei Zhu,Hirotaka Tamura,Masaya Kibune,Yasumoto Tomita,Takayuki Hamada,Masato Yoshioka,Kiyoshi Ishikawa,Takeshi Takayama,Junji Ogawa,Sanroku Tsukamoto,Tadahiro Kuroda +11 more
- 09 Oct 2009
TL;DR: A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch and a comparator with digital timing control offset cancellation is proposed.
148
A dynamic offset control technique for comparator design in scaled CMOS technology
Xiaolei Zhu,Yanfei Chen,Masaya Kibune,Yasumoto Tomita,Takayuki Hamada,Hirotaka Tamura,Sanroku Tsukamoto,Tadahiro Kuroda +7 more
- 17 Nov 2008
TL;DR: A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology and has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW.
17
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array
Xiaolei Zhu,Yanfei Chen,Sanroku Tsukamoto,Tadahiro Kuroda +3 more
- 23 Apr 2012
TL;DR: A partially asymmetric tri-level CDAC design technique is proposed to save the silicon cost and power as well and make it possible for the SAR ADC to achieve a 9-bit resolution with 4-bit + 3-bit split capacitor arrays.
17
1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator
Baoyong Chi,Xiaolei Zhu,Shutlong Huang,Zhihua Wang +3 more
- 18 Oct 2004
TL;DR: In this paper, a 1GHz monolithic high spectrum purity fractional-N frequency synthesizer with a 3-b third-order /spl Delta/spl Sigma/ modulator is implemented.
5
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
Xiaolei Zhu,Yanfei Chen,Masaya Kibune,Yasumoto Tomita,Takayuki Hamada,Hirotaka Tamura,Sanroku Tsukamoto,Tadahiro Kuroda +7 more
TL;DR: This work explores a dynamic offset control technique that employs charge compensation by timing control and proposes a simple method to generate offset compensation voltage by implementing two source-drain shorted transistors on each regenerative node with timing control signals on their gates.
4