25 Papers
251 Citations
Xi Chen is an academic researcher from University of Colorado Boulder. The author has contributed to research in topics: Computer science & Algorithm design. The author has an hindex of 13, co-authored 24 publications. Previous affiliations of Xi Chen include Northwestern University & University of Michigan.
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Papers
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
TL;DR: This work presents a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular, and reduces the proposed algorithm to a register transfer level hardware design, permitting performance, power consumption, and area estimation.
Reliability Modeling and Management of Nanophotonic On-Chip Networks
Zheng Li,Moustafa Mohamed,Xi Chen,Eric Dudley,Ke Meng,Li Shang,Alan R. Mickelson,Russ Joseph,Manish Vachharajani,Brian T. Schwartz,Yihe Sun +10 more
TL;DR: The paper first presents a model predicting the system-level effects of thermal and process variation in nanophotonic networks, and shows how to optimize many-core system performance and reliability by using run-time techniques to compensate for the thermal andprocess variation effects.
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Process variation in silicon photonic devices
TL;DR: An array of passive silicon-on-insulator optical devices is laid out in repeating patterns on four foundry-fabricated wafers and the process variation exhibits "random walk" pattern with spatial extent.
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Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
Zheng Li,Moustafa Mohamed,Xi Chen,Hongyu Zhou,Alan R. Mickelson,Li Shang,Manish Vachharajani +6 more
TL;DR: Iris, a CMOS-compatible high-performance low-power nanophotonic on- chip network, is introduced and offers an on-chip communication backplane that is power efficient while demonstrating low latency and high throughput.
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Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect
TL;DR: Simulation results indicate that the proposed reliability-aware design flow can fully compensate variations thereby sustaining reliable on-chip optical communication with power efficiency, and a multilevel reliability management solution is proposed.
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